@inproceedings{GiorgiB08-0,
  title = {Reducing Leakage through Filter Cache},
  author = {Roberto Giorgi and Paolo Bennati},
  year = {2008},
  doi = {10.1109/DSD.2008.123},
  url = {http://dx.doi.org/10.1109/DSD.2008.123},
  tags = {caching},
  researchr = {https://researchr.org/publication/GiorgiB08-0},
  cites = {0},
  citedby = {0},
  pages = {334-341},
  booktitle = {11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008},
  editor = {Luca Fanucci},
  publisher = {IEEE},
  isbn = {978-0-7695-3277-6},
}

@inproceedings{GiorgiB08,
  title = {Filtering drowsy instruction cache to achieve better efficiency},
  author = {Roberto Giorgi and Paolo Bennati},
  year = {2008},
  doi = {10.1145/1363686.1364050},
  url = {http://doi.acm.org/10.1145/1363686.1364050},
  tags = {caching},
  researchr = {https://researchr.org/publication/GiorgiB08},
  cites = {0},
  citedby = {0},
  pages = {1554-1555},
  booktitle = {Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), Fortaleza, Ceara, Brazil, March 16-20, 2008},
  editor = {Roger L. Wainwright and Hisham Haddad},
  publisher = {ACM},
  isbn = {978-1-59593-753-7},
}

@article{GiorgiP99,
  title = {PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors},
  author = {Roberto Giorgi and Cosimo Antonio Prete},
  year = {1999},
  url = {http://www.computer.org/tpds/td1999/l0742abs.htm},
  tags = {protocol},
  researchr = {https://researchr.org/publication/GiorgiP99},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. Parallel Distrib. Syst.},
  volume = {10},
  number = {7},
  pages = {742-763},
}

@article{FogliaGP05,
  title = {Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload},
  author = {Pierfrancesco Foglia and Roberto Giorgi and Cosimo Antonio Prete},
  year = {2005},
  doi = {10.1016/j.jpdc.2004.10.003},
  url = {http://dx.doi.org/10.1016/j.jpdc.2004.10.003},
  researchr = {https://researchr.org/publication/FogliaGP05},
  cites = {0},
  citedby = {0},
  journal = {J. Parallel Distrib. Comput.},
  volume = {65},
  number = {3},
  pages = {289-306},
}

@inproceedings{FogliaGP02,
  title = {Boosting the Performance of Three-Tier Web Servers Deploying SMP Architecture},
  author = {Pierfrancesco Foglia and Roberto Giorgi and Cosimo Antonio Prete},
  year = {2002},
  url = {http://link.springer.de/link/service/series/0558/bibs/2376/23760134.htm},
  tags = {deployment, architecture},
  researchr = {https://researchr.org/publication/FogliaGP02},
  cites = {0},
  citedby = {0},
  pages = {134-146},
  booktitle = {Web Engineering and Peer-to-Peer Computing, NETWORKING 2002 Workshops, Pisa, Italy, May 19-24, 2002, Revised Papers},
  editor = {Enrico Gregori and Ludmila Cherkasova and Gianpaolo Cugola and Fabio Panzieri and Gian Pietro Picco},
  volume = {2376},
  series = {Lecture Notes in Computer Science},
  publisher = {Springer},
  isbn = {3-540-44177-8},
}

@article{BranovicGM04,
  title = {A workload characterization of elliptic curve cryptography methods in embedded environments},
  author = {Irina Branovic and Roberto Giorgi and Enrico Martinelli},
  year = {2004},
  doi = {10.1145/1024295.1024299},
  url = {http://doi.acm.org/10.1145/1024295.1024299},
  tags = {Meta-Environment},
  researchr = {https://researchr.org/publication/BranovicGM04},
  cites = {0},
  citedby = {0},
  journal = {SIGARCH Computer Architecture News},
  volume = {32},
  number = {3},
  pages = {27-34},
}

@inproceedings{FogliaGP00,
  title = {Performance Analysis of Electronic Commerce Multiprocessor Server},
  author = {Pierfrancesco Foglia and Roberto Giorgi and Cosimo Antonio Prete},
  year = {2000},
  url = {http://computer.org/proceedings/hicss/0493/04936/04936059abs.htm},
  tags = {analysis},
  researchr = {https://researchr.org/publication/FogliaGP00},
  cites = {0},
  citedby = {0},
  booktitle = {HICSS},
}

@inproceedings{GiorgiPP09-0,
  title = {Exploiting DMA to enable non-blocking execution in Decoupled Threaded Architecture},
  author = {Roberto Giorgi and Zdravko Popovic and Nikola Puzovic},
  year = {2009},
  doi = {10.1109/IPDPS.2009.5161111},
  url = {http://dx.doi.org/10.1109/IPDPS.2009.5161111},
  tags = {architecture},
  researchr = {https://researchr.org/publication/GiorgiPP09-0},
  cites = {0},
  citedby = {0},
  pages = {1-8},
  booktitle = {23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009},
  publisher = {IEEE},
}

@article{KaviAG00,
  title = {Execution and Cache Performance of the Scheduled Dataflow Architecture},
  author = {Krishna M. Kavi and Joseph Arul and Roberto Giorgi},
  year = {2000},
  url = {http://www.jucs.org/jucs_6_10/execution_and_cache_performance},
  tags = {caching, architecture},
  researchr = {https://researchr.org/publication/KaviAG00},
  cites = {0},
  citedby = {0},
  journal = {J. UCS},
  volume = {6},
  number = {10},
  pages = {948-967},
}

@inproceedings{GiorgiPP09,
  title = {Introducing Hardware TLP Support in the Cell Processor},
  author = {Roberto Giorgi and Zdravko Popovic and Nikola Puzovic},
  year = {2009},
  doi = {10.1109/CISIS.2009.177},
  url = {http://doi.ieeecomputersociety.org/10.1109/CISIS.2009.177},
  researchr = {https://researchr.org/publication/GiorgiPP09},
  cites = {0},
  citedby = {0},
  pages = {657-662},
  booktitle = {CISIS},
}

@article{BartoliniGPPV01,
  title = {Parallel architecture and compilation techniques: selection of workshop papers, guests  editors introduction},
  author = {Sandro Bartolini and Roberto Giorgi and Jelica Protic and Cosimo Antonio Prete and M. Valero},
  year = {2001},
  doi = {10.1145/563647.563651},
  url = {http://doi.acm.org/10.1145/563647.563651},
  tags = {architecture},
  researchr = {https://researchr.org/publication/BartoliniGPPV01},
  cites = {0},
  citedby = {0},
  journal = {SIGARCH Computer Architecture News},
  volume = {29},
  number = {5},
  pages = {9-12},
}

@inproceedings{GiorgiPP09-1,
  title = {Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture},
  author = {Roberto Giorgi and Zdravko Popovic and Nikola Puzovic},
  year = {2009},
  doi = {10.1007/978-3-642-03138-0_9},
  url = {http://dx.doi.org/10.1007/978-3-642-03138-0_9},
  tags = {architecture},
  researchr = {https://researchr.org/publication/GiorgiPP09-1},
  cites = {0},
  citedby = {0},
  pages = {78-87},
  booktitle = {Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings},
  editor = {Koen Bertels and Nikitas J. Dimopoulos and Cristina Silvano and Stephan Wong},
  volume = {5657},
  series = {Lecture Notes in Computer Science},
  publisher = {Springer},
  isbn = {978-3-642-03137-3},
}

@inproceedings{GiorgiPPAJ08,
  title = {Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture},
  author = {Roberto Giorgi and Zdravko Popovic and Nikola Puzovic and Arnaldo Azevedo and Ben H. H. Juurlink},
  year = {2008},
  doi = {10.1109/DSD.2008.93},
  url = {http://dx.doi.org/10.1109/DSD.2008.93},
  tags = {architecture},
  researchr = {https://researchr.org/publication/GiorgiPPAJ08},
  cites = {0},
  citedby = {0},
  pages = {189-194},
  booktitle = {11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008},
  editor = {Luca Fanucci},
  publisher = {IEEE},
  isbn = {978-0-7695-3277-6},
}

@inproceedings{BartoliniBGM04,
  title = {A Performance Evaluation of ARM ISA Extension for Elliptic Curve Cryptography over Binary Finite Fields},
  author = {Sandro Bartolini and Irina Branovic and Roberto Giorgi and Enrico Martinelli},
  year = {2004},
  url = {http://csdl.computer.org/comp/proceedings/sbac-pad/2004/2240/00/22400238abs.htm},
  researchr = {https://researchr.org/publication/BartoliniBGM04},
  cites = {0},
  citedby = {0},
  pages = {238-245},
  booktitle = {16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 27-29 October 2004, Foz do Iguacu, Brazil},
  publisher = {IEEE Computer Society},
  isbn = {0-7695-2240-8},
}

@inproceedings{GiorgiPP07,
  title = {DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems},
  author = {Roberto Giorgi and Zdravko Popovic and Nikola Puzovic},
  year = {2007},
  doi = {10.1109/SBAC-PAD.2007.19},
  url = {http://doi.ieeecomputersociety.org/10.1109/SBAC-PAD.2007.19},
  tags = {architecture, C++},
  researchr = {https://researchr.org/publication/GiorgiPP07},
  cites = {0},
  citedby = {0},
  pages = {263-270},
  booktitle = {19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 24-27 October 2007, Gramado, RS, Brazil},
  publisher = {IEEE Computer Society},
}

@article{KaviGA01,
  title = {Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation},
  author = {Krishna M. Kavi and Roberto Giorgi and Joseph Arul},
  year = {2001},
  url = {http://www.computer.org/tc/tc2001/t0834abs.htm},
  tags = {architecture},
  researchr = {https://researchr.org/publication/KaviGA01},
  cites = {0},
  citedby = {0},
  journal = {IEEE Transactions on Computers},
  volume = {50},
  number = {8},
  pages = {834-846},
}

@article{FogliaGP04,
  title = {Speeding-up multiprocessors running DBMS workloads through coherence protocols},
  author = {Pierfrancesco Foglia and Roberto Giorgi and Cosimo Antonio Prete},
  year = {2004},
  doi = {10.1504/IJHPCN.2004.007562},
  url = {http://dx.doi.org/10.1504/IJHPCN.2004.007562},
  tags = {protocol},
  researchr = {https://researchr.org/publication/FogliaGP04},
  cites = {0},
  citedby = {0},
  journal = {IJHPCN},
  volume = {1},
  number = {1/2/3},
  pages = {17-32},
}

@inproceedings{KaviAG01,
  title = {Performance Evaluation of a Non-Blocking Multithreaded Architecture for Embedded, Real-Time and DSP Applications},
  author = {Krishna M. Kavi and Joseph Arul and Roberto Giorgi},
  year = {2001},
  tags = {architecture},
  researchr = {https://researchr.org/publication/KaviAG01},
  cites = {0},
  citedby = {0},
  pages = {365-371},
  booktitle = {Proceedings of the ISCA 14th International Conference on Parallel and Distributed Computing Systems, August 8-10, 2001, Richardson, Texas, USA},
  editor = {Edwin Hsing-Mean Sha},
  publisher = {ISCA},
  isbn = {1-880843-39-0},
}

@inproceedings{GiorgiPRP96,
  title = {A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors},
  author = {Roberto Giorgi and Cosimo Antonio Prete and Luigi M. Ricciardi and Gianpaolo Prina},
  year = {1996},
  url = {http://csdl.computer.org/comp/proceedings/euromicro/1996/7487/00/74870207abs.htm},
  tags = {systematic-approach},
  researchr = {https://researchr.org/publication/GiorgiPRP96},
  cites = {0},
  citedby = {0},
  pages = {207-214},
  booktitle = {22rd EUROMICRO Conference  96, Beyond 2000: Hardware and Software Design Strategies,  September 2-5, 1996, Prague, Czech Republic},
  publisher = {IEEE Computer Society},
}

@article{BartoliniBGM08,
  title = {Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2/sup m/)},
  author = {Sandro Bartolini and Irina Branovic and Roberto Giorgi and Enrico Martinelli},
  year = {2008},
  doi = {10.1109/TC.2007.70832},
  url = {http://doi.ieeecomputersociety.org/10.1109/TC.2007.70832},
  tags = {case study},
  researchr = {https://researchr.org/publication/BartoliniBGM08},
  cites = {0},
  citedby = {0},
  journal = {IEEE Transactions on Computers},
  volume = {57},
  number = {5},
  pages = {672-685},
}

@inproceedings{GiorgiPPR97,
  title = {A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessors},
  author = {Roberto Giorgi and Cosimo Antonio Prete and Gianpaolo Prina and Luigi M. Ricciardi},
  year = {1997},
  url = {http://csdl.computer.org/comp/proceedings/hicss/1997/7734/01/7734010266abs.htm},
  tags = {meta-model, Meta-Environment, meta-objects},
  researchr = {https://researchr.org/publication/GiorgiPPR97},
  cites = {0},
  citedby = {0},
  pages = {266-275},
  booktitle = {HICSS (3)},
}

@article{BartoliniG06,
  title = {Issues in Embedded Single-Chip Multicore Architectures},
  author = {Sandro Bartolini and Roberto Giorgi},
  year = {2006},
  url = {http://iospress.metapress.com/content/agxunaaln3804nr1/},
  tags = {architecture},
  researchr = {https://researchr.org/publication/BartoliniG06},
  cites = {0},
  citedby = {0},
  journal = {J. Embedded Computing},
  volume = {2},
  number = {2},
  pages = {137-139},
}

@inproceedings{FogliaGP01,
  title = {Evaluating Optimizing for Multiprocessors E-Commerce Server Running TPC-W Workload},
  author = {Pierfrancesco Foglia and Roberto Giorgi and Cosimo Antonio Prete},
  year = {2001},
  url = {http://computer.org/proceedings/hicss/0981/volume 207/09817046abs.htm},
  tags = {optimization, e-science},
  researchr = {https://researchr.org/publication/FogliaGP01},
  cites = {0},
  citedby = {0},
  booktitle = {HICSS},
}

@inproceedings{FogliaGP99,
  title = {Process Migration Effects on Memory Performance of Multiprocessor},
  author = {Pierfrancesco Foglia and Roberto Giorgi and Cosimo Antonio Prete},
  year = {1999},
  tags = {migration},
  researchr = {https://researchr.org/publication/FogliaGP99},
  cites = {0},
  citedby = {0},
  pages = {133-142},
  booktitle = {High Performance Computing - HiPC 99, 6th International Conference, Calcutta, India, December 17-20, 1999, Proceedings},
  editor = {Prithviraj Banerjee and Viktor K. Prasanna and Bhabani P. Sinha},
  volume = {1745},
  series = {Lecture Notes in Computer Science},
  publisher = {Springer},
  isbn = {3-540-66907-8},
}