publications:
- title: "Fine grain thermal modeling and experimental validation of 3D-ICs"
  author:
  - name: "Oprins, H."
    link: "https://researchr.org/alias/oprins%2C-h."
  - name: "Adi Srinivasan"
    link: "http://www.caltech.edu"
  - name: "Cupak, M."
    link: "https://researchr.org/alias/cupak%2C-m."
  - name: "Cherman, V."
    link: "https://researchr.org/alias/cherman%2C-v."
  - name: "Torregiani, C."
    link: "https://researchr.org/alias/torregiani%2C-c."
  - name: "Stucchi, M."
    link: "https://researchr.org/alias/stucchi%2C-m."
  - name: "{Van der Plas}, G."
    link: "https://researchr.org/alias/%7Bvan-der-plas%7D%2C-g."
  - name: "Marchal, P."
    link: "https://researchr.org/alias/marchal%2C-p."
  - name: "Vandevelde, B."
    link: "https://researchr.org/alias/vandevelde%2C-b."
  - name: "Cheng, E."
    link: "https://researchr.org/alias/cheng%2C-e."
  year: "2011"
  month: "April"
  doi: "http://dx.doi.org/10.1016/j.mejo.2010.08.006"
  abstract: "3D die stacking is a promising technique to allow miniaturization and performance enhancement of electronic systems. Key technologies for realizing 3D interconnect schemes are the realization of vertical connections, either through the Si die or through the multilayer interconnections. The complexity of these structures combined with reduced thermal spreading in the thinned dies complicate the thermal analysis of a stacked die structure. In this paper a methodology is presented to perform a detailed thermal analysis of stacked die packages including the complete back end of line structure (BEOL), interconnection between the dies and the complete electrical design layout of all the stacked dies. The calculations are performed by 3D numerical techniques and the approach allows importing the full electrical design of all the dies in the stack. The methodology is demonstrated on a 2 stacked die structure in a BGA package. For this case the influence of through-Si vias (TSVs) on the temperature distribution is studied. The modeling results are experimentally validated with a dedicated test vehicle. A thermal test chip with integrated heaters and diodes as thermals sensors is used to successfully validate the detailed temperature profile of the hot spots in the top die of the die stack."
  links:
    doi: "http://dx.doi.org/10.1016/j.mejo.2010.08.006"
    "url": "http://dx.doi.org/10.1016/j.mejo.2010.08.006"
  tags:
  - "completeness"
  - "layout"
  - "meta-model"
  - "modeling"
  - "design complexity"
  - "testing"
  - "analysis"
  - "C++"
  - "Meta-Environment"
  - "design"
  - "systematic-approach"
  researchr: "https://researchr.org/publication/Oprins2010"
  cites: 0
  citedby: 0
  journal: "mj"
  volume: "42"
  number: "4"
  pages: "572-578"
  kind: "article"
  key: "Oprins2010"
- title: "Practical chip-centric electro-thermal simulations"
  author:
  - name: "Gillon, Renaud"
    link: "https://researchr.org/alias/gillon%2C-renaud"
  - name: "Joris, Patricia"
    link: "https://researchr.org/alias/joris%2C-patricia"
  - name: "Oprins, Herman"
    link: "https://researchr.org/alias/oprins%2C-herman"
  - name: "Vandevelde, Bart"
    link: "https://researchr.org/alias/vandevelde%2C-bart"
  - name: "Adi Srinivasan"
    link: "http://www.caltech.edu"
  - name: "Chandra, Rajit"
    link: "https://researchr.org/alias/chandra%2C-rajit"
  year: "2008"
  month: "sep"
  doi: "http://dx.doi.org/10.1109/THERMINIC.2008.4669912"
  links:
    doi: "http://dx.doi.org/10.1109/THERMINIC.2008.4669912"
    "url": "http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=4669912"
  researchr: "https://researchr.org/publication/Gillon2008"
  cites: 0
  citedby: 0
  journal: "2008 14th International Workshop on Thermal Inveatigation of ICs and Systems"
  number: "September"
  pages: "220-223"
  kind: "article"
  key: "Gillon2008"
- title: "A 1024 Pin Universal Interconnect Array With Routing Architecture"
  author:
  - name: "Guo, R."
    link: "https://researchr.org/alias/guo%2C-r."
  - name: "Adi Srinivasan"
    link: "http://www.caltech.edu"
  - name: "Verheyen, H."
    link: "https://researchr.org/alias/verheyen%2C-h."
  - name: "Law, S."
    link: "https://researchr.org/alias/law%2C-s."
  - name: "Mohsen, A."
    link: "https://researchr.org/alias/mohsen%2C-a."
  year: "1992"
  doi: "http://dx.doi.org/10.1109/CICC.1992.591112"
  links:
    doi: "http://dx.doi.org/10.1109/CICC.1992.591112"
    "url": "http://ieeexplore.ieee.org/xpl/freeabs\\_all.jsp?arnumber=591112"
  tags:
  - "architecture"
  - "routing"
  researchr: "https://researchr.org/publication/Guo-0"
  cites: 0
  citedby: 0
  edition: "Proceedings of the IEEE Custom Integrated Circuits Conference"
  publisher: "IEEE Proceedings of Custom Integrated Circuits Conference"
  isbn: "0-7803-0246-X"
  kind: "book"
  key: "Guo-0"
- title: "Investigation of tier-swapping to improve the thermal profile of memory-on-logic 3DICs"
  author:
  - name: "Melamed, Samson"
    link: "https://researchr.org/alias/melamed%2C-samson"
  - name: "Thorolfsson, Thorlindur"
    link: "https://researchr.org/alias/thorolfsson%2C-thorlindur"
  - name: "Adi Srinivasan"
    link: "http://www.caltech.edu"
  - name: "Cheng, Edmund"
    link: "https://researchr.org/alias/cheng%2C-edmund"
  - name: "Franzon, Paul"
    link: "https://researchr.org/alias/franzon%2C-paul"
  - name: "Davis, W. Rhett"
    link: "https://researchr.org/alias/davis%2C-w.-rhett"
  year: "2010"
  abstract: "In 3DICs heat dissipating devices are stacked directly on top of each other leading to a higher heat density than in a comparable 2D chip. 3D integration also moves the majority of active devices further away from the heatsink. This results in a degraded thermal path which makes it more challenging to remove heat from the active devices. Gradient HeatWave-3DIC was used to perform an appropriate 3D thermal analysis on a 1024-point, memory-on-logic 3DIC FFT processor for synthetic aperture radar (SAR). The chip was simulated with a spatial resolution of 80 nm, and was modeled to include the effect of each line of interconnect, as well as each via and fill structure exactly as drawn in the layout. Large isolated temperature spikes were found near groups of clock buffers at the edge of the SRAMs on the middle tier. The effect of reordering the stackup of memory and logic tiers has been investigated. It was found that placing the memory tier closer to the heatsink improved not only the thermal profile of the memories but also of the logic tiers. Temperature spikes in the memories no longer significantly impacted the logic tiers, yielding a design where the thermal profile of the tiers were significantly less dependent on each other."
  links:
    "url": "http://ieeexplore.ieee.org/xpl/freeabs\\_all.jsp?arnumber=5636308"
  tags:
  - "layout"
  - "meta-model"
  - "analysis"
  - "logic"
  - "Meta-Environment"
  - "design"
  - "process modeling"
  researchr: "https://researchr.org/publication/Melamed"
  cites: 0
  citedby: 0
  journal: "Thermal Investigations of ICs and Systems (THERMINIC), 2010 16th International Workshop on"
  pages: "1-6"
  kind: "article"
  key: "Melamed"
- title: "A novel reprogrammable interconnect architecture with decoded RAM storage"
  author:
  - name: "Guo, R."
    link: "https://researchr.org/alias/guo%2C-r."
  - name: "Nguyen, H."
    link: "https://researchr.org/alias/nguyen%2C-h."
  - name: "Adi Srinivasan"
    link: "http://www.caltech.edu"
  - name: "Nasir, Q."
    link: "https://researchr.org/alias/nasir%2C-q."
  - name: "Cai, H."
    link: "https://researchr.org/alias/cai%2C-h."
  - name: "Law, S."
    link: "https://researchr.org/alias/law%2C-s."
  - name: "Mohsen, A."
    link: "https://researchr.org/alias/mohsen%2C-a."
  year: "1994"
  doi: "http://dx.doi.org/10.1109/CICC.1994.379738"
  abstract: "Using a new architecture and routing scheme, a second generation 1024 pin interconnect device features up to 40\\% die size reduction and twice the speed. A novel decoded RAM storage and 5 T RAM cell yield the area reduction. The new architecture also adds 256 buffers. Unbuffered paths are passive and bi-directional. The programming time of on-chip memory also improves dramatically from 40 ms to less than 1 ms"
  links:
    doi: "http://dx.doi.org/10.1109/CICC.1994.379738"
    "url": "http://ieeexplore.ieee.org/xpl/freeabs\\_all.jsp?arnumber=379738"
  tags:
  - "architecture"
  - "programming"
  - "routing"
  researchr: "https://researchr.org/publication/Guo"
  cites: 0
  citedby: 0
  edition: "Proceedings of IEEE Custom Integrated Circuits Conference"
  publisher: "IEEE Proceedings of Custom Integrated Circuits Conference"
  isbn: "0-7803-1886-2"
  kind: "book"
  key: "Guo"
- title: "Non-orthogonal decoding: An architectural element for reprogrammable interconnect or logic"
  author:
  - name: "Adi Srinivasan"
    link: "http://www.caltech.edu"
  year: "1996"
  doi: "http://dx.doi.org/10.1109/CICC.1996.510533"
  abstract: "A reprogrammable logic or interconnect architecture termed non-orthogonal decoding is described, which increases routability with no additional circuitry and negligible added layout area, compared to an existing reprogrammable routing architecture, the orthogonal decoding architecture introduced by Aptix. An orthogonal decoding architecture's routing channel box is modified to illustrate non-orthogonal decoding. The former is shown to be replaceable, without restrictions, by non-orthogonal decoding, which is also shown to increase routability. A generalization of the 2-d decoding space to higher dimensions and the application of non-orthogonal decoding to FPGAs are discussed"
  links:
    doi: "http://dx.doi.org/10.1109/CICC.1996.510533"
    "url": "http://ieeexplore.ieee.org/xpl/freeabs\\_all.jsp?arnumber=510533"
  tags:
  - "layout"
  - "architecture"
  - "logic"
  - "routing"
  researchr: "https://researchr.org/publication/Srinivasan"
  cites: 0
  citedby: 0
  publisher: "IEEE Proceedings of Custom Integrated Circuits Conference"
  isbn: "0-7803-3117-6"
  kind: "book"
  key: "Srinivasan"
- title: "Fine grain thermal modeling of 3D stacked structures"
  author:
  - name: "Oprins, H."
    link: "https://researchr.org/alias/oprins%2C-h."
  - name: "Cupak, M."
    link: "https://researchr.org/alias/cupak%2C-m."
  - name: "{Van der Plas}, G."
    link: "https://researchr.org/alias/%7Bvan-der-plas%7D%2C-g."
  - name: "Marchal, P."
    link: "https://researchr.org/alias/marchal%2C-p."
  - name: "Vandevelde, B."
    link: "https://researchr.org/alias/vandevelde%2C-b."
  - name: "Adi Srinivasan"
    link: "http://www.caltech.edu"
  - name: "Cheng, E."
    link: "https://researchr.org/alias/cheng%2C-e."
  year: "2009"
  abstract: "3D stacking of dies is a promising technique to allow miniaturization and performance enhancement of electronic systems. Key technologies for realizing 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnections. The complexity of these structures combined with reduced thermal spreading in the thinned dies complicate the thermal analysis of a stacked die structure. In this paper a methodology is presented to perform a detailed thermal analysis of stacked die packages including the complete back end of line structure (BEOL), interconnection between the dies and the complete electrical design layout of all the stacked dies. The calculations are performed by 3D numerical techniques and the approach allows importing the full electrical design of all the dies in the stack. The methodology is demonstrated on a 2 stacked die structure in a BGA package. For this case the influence of through-Si vias (TSVs) on the temperature distribution is studied."
  links:
    "url": "http://ieeexplore.ieee.org/xpl/freeabs\\_all.jsp?arnumber=5340064"
  tags:
  - "completeness"
  - "layout"
  - "modeling"
  - "design complexity"
  - "analysis"
  - "design"
  - "systematic-approach"
  researchr: "https://researchr.org/publication/Oprinsa"
  cites: 0
  citedby: 0
  journal: "Thermal Investigations of ICs and Systems, 2009. THERMINIC 2009. 15th International Workshop on"
  pages: "45-49"
  kind: "article"
  key: "Oprinsa"
- title: "Junction-level thermal extraction and simulation of 3DICs"
  author:
  - name: "Samson Melamed"
    link: "https://researchr.org/alias/samson-melamed"
  - name: "Thorlindur Thorolfsson"
    link: "https://researchr.org/alias/thorlindur-thorolfsson"
  - name: "Adi Srinivasan"
    link: "http://www.caltech.edu"
  - name: "Edmund Cheng"
    link: "https://researchr.org/alias/edmund-cheng"
  - name: "Paul Franzon"
    link: "https://researchr.org/alias/paul-franzon"
  - name: "Rhett Davis"
    link: "https://researchr.org/alias/rhett-davis"
  year: "2009"
  doi: "http://dx.doi.org/10.1109/3DIC.2009.5306529"
  links:
    doi: "http://dx.doi.org/10.1109/3DIC.2009.5306529"
  researchr: "https://researchr.org/publication/MelamedTSCFD09"
  cites: 0
  citedby: 0
  pages: "1-7"
  booktitle: "3dic"
  kind: "inproceedings"
  key: "MelamedTSCFD09"
- title: "Experimental characterization and model validation of thermal hot spots in 3D stacked ICs"
  author:
  - name: "Oprins, H."
    link: "https://researchr.org/alias/oprins%2C-h."
  - name: "Cherman, V."
    link: "https://researchr.org/alias/cherman%2C-v."
  - name: "Adi Srinivasan"
    link: "http://www.caltech.edu"
  - name: "Cupak, M."
    link: "https://researchr.org/alias/cupak%2C-m."
  - name: "{Van der Plas}, G."
    link: "https://researchr.org/alias/%7Bvan-der-plas%7D%2C-g."
  - name: "Marchal, P."
    link: "https://researchr.org/alias/marchal%2C-p."
  - name: "Vandevelde, B."
    link: "https://researchr.org/alias/vandevelde%2C-b."
  - name: "Cheng, E."
    link: "https://researchr.org/alias/cheng%2C-e."
  year: "2010"
  abstract: "3D stacking of dies is a promising technique to allow miniaturization and performance enhancement of electronic systems. Key technologies for realizing 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnections. The major bottleneck for 3D integration are thermal management issues due to the reduced thermal spreading in the thinned dies and the poor thermally conductive adhesives. In this paper, a dedicated thermal test vehicle with integrated heaters and sensors is presented to experimentally characterize the thermal behavior in 3D stacks. This test vehicle is used to validate a presented methodology for fine grain thermal analysis in 3D-ICs."
  links:
    "url": "http://ieeexplore.ieee.org/xpl/freeabs\\_all.jsp?arnumber=5636338"
  tags:
  - "testing"
  - "analysis"
  researchr: "https://researchr.org/publication/Oprins"
  cites: 0
  citedby: 0
  journal: "Thermal Investigations of ICs and Systems (THERMINIC), 2010 16th International Workshop on"
  pages: "1-5"
  kind: "article"
  key: "Oprins"