| 273 | -- | 278 | Hossein Aghababa, Alireza Khosropour, Ali Afzali-Kusha, Behjat Forouzandeh, Massoud Pedram. Statistical estimation of leakage power dissipation in nano-scale complementary metal oxide semiconductor digital circuits using generalised extreme value distribution |
| 279 | -- | 286 | Ahmed Yasir Dogan, Jeremy Constantin, David Atienza, Andreas Burg, Luca Benini. Low-power processor architecture exploration for online biomedical signal analysis |
| 287 | -- | 296 | Ons Mbarek, Alain Pegatoquet, Michel Auguin. Using unified power format standard concepts for power-aware design and verification of systems-onchip at transaction level |
| 297 | -- | 307 | Lars Schor, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele. Worst-case temperature analysis for different resource models |
| 308 | -- | 321 | Amir-Mohammad Rahmani, Kameswar Rao Vaddina, Khalid Latif 0002, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. Design and management of high-performance, reliable and thermal-aware 3D networks-on-chip |
| 322 | -- | 329 | Ignacio Arnaldo, José Luis Risco-Martín, José Luis Ayala, José Ignacio Hidalgo. Power profiling-guided floorplanner for 3D multi-processor systems-on-chip |
| 330 | -- | 337 | Ning Chen, Bing Li, Ulf Schlichtmann. Iterative timing analysis based on nonlinear and interdependent flipflop modelling |
| 338 | -- | 346 | Tomislav Matic, Tomislav Svedek, Davor Vinko. Integrator clamping for asynchronous sigma-delta modulator central frequency increment |
| 347 | -- | 354 | Bruno Vaquie, Sébastien Tiran, Philippe Maurine. Secure D flip-flop against side channel attacks |
| 355 | -- | 365 | Omer Khan, Sandip Kundu. Empirical model for cooperative resizing of processor structures to exploit power-performance efficiency at runtime |
| 366 | -- | 373 | Hossein Karimiyan Alidash, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino. On-chip process variation-tracking through an all-digital monitoring architecture |