Journal: JETC

Volume 12, Issue 4

31 -- 0Hoda Aghaei Khouzani, Yuan Xue, Chengmo Yang. Fully Exploiting PCM Write Capacity Within Near Zero Cost Through Segment-Based Page Allocation
32 -- 0Christophe Layer, Laurent Becker, Kotb Jabeur, Sylvain Claireux, Bernard Dieny, Guillaume Prenat, Gregory di Pendina, Stephane Gros, Pierre Paoli, Virgile Javerliac, Fabrice Bernard-Granger, Loïc Decloedt. Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories
33 -- 0Chengwen Wu, Guangyan Zhang, Keqin Li. Rethinking Computer Architectures and Software Systems for Phase-Change Memory
34 -- 0Arighna Deb, Debesh K. Das, Hafizur Rahaman, Robert Wille, Rolf Drechsler, Bhargab B. Bhattacharya. Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability
35 -- 0Qian Wang, Yongtae Kim, Peng Li. Neuromorphic Processors with Memristive Synapses: Synaptic Interface and Architectural Exploration
36 -- 0Kalyan Biswas, Angsuman Sarkar, Chandan Kumar Sarkar. Impact of Fin Width Scaling on RF/Analog Performance of Junctionless Accumulation-Mode Bulk FinFET
37 -- 0Yi-Hang Chen, Jian-Yu Chen, Juinn-Dar Huang. Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints
38 -- 0Moon Seok Kim, William Cane-Wissing, Xueqing Li, Jack Sampson, Suman Datta, Sumeet Kumar Gupta, Vijaykrishnan Narayanan. Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells
39 -- 0Muhammad Ahsan, Rodney Van Meter, Jungsang Kim. Designing a Million-Qubit Quantum Computer Using a Resource Performance Simulator
40 -- 0Mona Arabzadeh, Mahboobeh Houshmand, Mehdi Sedighi, Morteza Saheb Zamani. Quantum-Logic Synthesis of Hermitian Gates
41 -- 0Mathias Soeken, Robert Wille, Oliver Keszocze, D. Michael Miller, Rolf Drechsler. Embedding of Large Boolean Functions for Reversible Logic
42 -- 0Aoxiang Tang, Xun Gao, Lung-Yen Chen, Niraj K. Jha. Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations: Observing the Trends between the 22nm and 14nm Technology Nodes
43 -- 0Sourindra M. Chaudhuri, Niraj K. Jha. Ultra-Low-Leakage and High-Performance Logic Circuit Design Using Multiparameter Asymmetric FinFETs
44 -- 0Anja von Beuningen, Luca Ramini, Davide Bertozzi, Ulf Schlichtmann. PROTON+: A Placement and Routing Tool for 3D Optical Networks-on-Chip with a Single Optical Layer
45 -- 0Abbas Dehghani 0002, Kamal Jamshidi. A Novel Approach to Optimize Fault-Tolerant Hybrid Wireless Network-on-Chip Architectures
46 -- 0Sparsh Mittal. A Survey of Architectural Techniques for Near-Threshold Computing