Journal: IEEE Trans. on Circuits and Systems

Volume 56-II, Issue 8

613 -- 0Anthony Chan Carusone, Un-Ku Moon. Introducing Jump-Start Tutorials
614 -- 618Dongwon Kwon, Gabriel A. Rincón-Mora. Single-Inductor-Multiple-Output Switching DC-DC Converters
619 -- 623Kamal El-Sankary, Hamed Hanafi Alamdari, Ezz I. El-Masry. An Adaptive ELD Compensation Technique Using a Predictive Comparator
624 -- 628Jean-François Bousquet, Sebastian Magierowski, Geoffrey G. Messier. An Integrated Active Reflector for Phase-Sweep Cooperative Diversity
629 -- 633Francisco Colodro Ruiz, Antonio Jesús Torralba Silgado, Jose Luis Mora, Juana Maria Martinez-Heredia. An Analog Squaring Technique Based on Asynchronous Sigma-Delta Modulation
634 -- 638Cheng C. Wang, Dejan Markovic. Delay Estimation and Sizing of CMOS Logic Using Logical Effort With Slope Correction
639 -- 643Noha Younis, Mahmoud Ashour, Amin Nassar. Power-Efficient Clock/Data Distribution Technique for Polyphase Comb Filter in Digital Receivers
644 -- 648Katsuki Kobayashi, Naofumi Takagi. m Based on the Extended Euclid's Algorithm With Parallelization of Modular Reductions
649 -- 653Young-Won Kim, Joo-Seong Kim, Jae-Hyuk Oh, Yoon-Suk Park, Jong Woo Kim, Kwang-Il Park, Bai-Sun Kong, Young-Hyun Jun. Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation
654 -- 658Zhan-Li Sun. An Extension of MISEP for Post-Nonlinear-Linear Mixture Separation
659 -- 663Shen-Ping Xiao, Xian-Ming Zhang. New Globally Asymptotic Stability Criteria for Delayed Cellular Neural Networks
664 -- 668Guofeng Zhang, Wei Xing Zheng. Stability and Bifurcation Analysis of a Class of Networked Dynamical Systems
669 -- 673Wei Zhou, Jacek M. Zurada. Discrete-Time Recurrent Neural Networks With Complex-Valued Linear Threshold Neurons
674 -- 678Antonio Loría. A Linear Time-Varying Controller for Synchronization of LÜ Chaotic Systems With One Input
679 -- 683Zhisheng Duan, Guanrong Chen. Global Robust Stability and Synchronization of Networks With Lorenz-Type Nodes
684 -- 686Hao Chen. CRT-Based High-Speed Parallel Architecture for Long BCH Encoding