Journal: IEEE Trans. on Circuits and Systems

Volume 57-II, Issue 9

661 -- 665Domenico Zito, Alessandro Fonte. Dual-Input Pseudo-Switch RF Low Noise Amplifier
666 -- 670Jung-Yu Chang, Shen-Iuan Liu. A Phase-Locked Loop With Background Leakage Current Compensation
671 -- 675Salvatore Levantino, Luca Collamati, Carlo Samori, Andrea L. Lacaita. Folding of Phase Noise Spectra in Charge-Pump Phase-Locked Loops Induced by Frequency Division
676 -- 680Vikas Singh, Nagendra Krishnapura, Shanthi Pavan. Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time DeltaSigma Modulators
681 -- 685Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya. circhboxC Current Reference Circuit Consisting of Subthreshold CMOS Circuits
686 -- 690Chen Zheng, Dongsheng Ma. Design of Monolithic Low Dropout Regulator for Wireless Powered Brain Cortical Implants Using a Line Ripple Rejection Technique
691 -- 695Hyunjoong Lee, Jong-Kwan Woo, Hyo-Jin Nam, Won-Hyeog Jin, Moongi Jeong, Young-Sik Kim, Jin-Koog Shin, Suhwan Kim. Charge Amplifier With an Enhanced Frequency Response for SPM-Based Data Storage
696 -- 700M. N. S. Swamy. Transpose of a Multiterminal Element and Applications
701 -- 705Liang Liu, Fan Ye, Xiaojing Ma, Tong Zhang 0002, Junyan Ren. A 1.1-Gb/s 115-pJ/bit Configurable MIMO Detector Using 0.13- muhboxm CMOS Technology
706 -- 710Ernst Martin Witte, Filippo Borlenghi, Gerd Ascheid, Rainer Leupers, Heinrich Meyr. A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding
711 -- 715Shin-Chi Lai, Sheau-Fang Lei, Wen-Ho Juang, Ching-Hsing Luo. A Low-Cost, Low-Complexity, and Memory-Free Architecture of Novel Recursive DFT and IDFT Algorithms for DTMF Application
716 -- 720Md. Ashraful Islam, Khan A. Wahid. Area- and Power-Efficient Design of Daubechies Wavelet Transforms Using Folded AIQ Mapping
721 -- 724Sven Lütkemeier, Ulrich Rückert. A Subthreshold to Above-Threshold Level Shifter Comprising a Wilson Current Mirror
725 -- 729Masoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi. Multiple Error Detection in DNA Self-Assembly Using Coded Tiles
730 -- 734Jessica R. Piper, J. C. Sprott. Simple Autonomous Chaotic Circuits
735 -- 739Z. Q. Zhu, H. P. Hu. Robust Synchronization by Time-Varying Impulsive Control
740 -- 744B. Liao, Z. G. Zhang, Shing-Chow Chan. A New Robust Kalman Filter-Based Subspace Tracking Algorithm in an Impulsive Noise Environment
745 -- 749Goran Molnar, Mladen Vucic. Noncausal IIR Fractional Hilbert Transformers With Equiripple or Flat Phase Response
750 -- 755Boyuan Yan, Sheldon X.-D. Tan, Jeffrey Fan. Passive Rational Interpolation-Based Reduction via Carathéodory Extension for General Systems

Volume 57-II, Issue 8

577 -- 581Yannis P. Tsividis. Event-Driven Data Acquisition and Digital Signal Processing - A Tutorial
582 -- 586Kuang-Chi He, Ming-Tsung Li, Chen-Ming Li, Jenn-Hwan Tarng. Parallel-RC Feedback Low-Noise Amplifier for UWB Applications
587 -- 591Md. Mahbub Reja, Kambiz K. Moez, Igor M. Filanovsky. An Area-Efficient Multistage 3.0- to 8.5-GHz CMOS UWB LNA Using Tunable Active Inductors
592 -- 596Sleiman Ball Sleiman, Mohammed Ismail. Multimode Reconfigurable Digital SigmaDelta Modulator Architecture for Fractional-N PLLs
597 -- 601Gang-Neng Sung, Szu-Chia Liao, Jian-Ming Huang, Yu-Cheng Lu, Chua-Chin Wang. All-Digital Frequency Synthesizer Using a Flying Adder
602 -- 606Kailash Chandrashekar, Marco Corsi, John Fattaruso, Bertan Bakkaloglu. A 20-MS/s to 40-MS/s Reconfigurable Pipeline ADC Implemented With Parallel OTA Scaling
607 -- 611U-Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti. Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC
612 -- 616Chua-Chin Wang, Ron-Chi Kuo, Jen-Wei Liu. 0.9 V to 5 V Bidirectional Mixed-Voltage I/O Buffer With an ESD Protection Output Stage
617 -- 621Xiaoman Wang, Baoyong Chi, Zhihua Wang. A Low-Power High-Data-Rate ASK IF Receiver With a Digital-Control AGC Loop
622 -- 626Francisco Colodro Ruiz, Antonio Jesús Torralba Silgado. Spectral Analysis of Pulsewidth-Modulated Sampled Signals
627 -- 631Dong Wang, Milos D. Ercegovac, Nanning Zheng. Design of High-Throughput Fixed-Point Complex Reciprocal/Square-Root Unit
632 -- 636Ji-Woong Choi, Jungwon Lee, Byung-Gueon Min, Jongsun Park. Energy Efficient Hardware Architecture of LU Triangularization for MIMO Receiver
637 -- 641Shih-Chang Hsia, Wen-Hsien Liao. Forward Computations for Context-Adaptive Variable-Length Coding Design
642 -- 646Patrick Yin Chiang, Changhui Hu. Chaotic Pulse-Position Baseband Modulation for an Ultra-Wideband Transceiver in CMOS
647 -- 651Shin-Chi Lai, Wen-Ho Juang, Chia-Lin Chang, Chen-Chieh Lin, Ching-Hsing Luo, Sheau-Fang Lei. Low-Computation-Cycle, Power-Efficient, and Reconfigurable Design of Recursive DFT for Portable Digital Radio Mondiale Receiver
652 -- 656Sanghoon Park, Lawrence E. Larson, Laurence B. Milstein. An RF Receiver Detection Technique for Cognitive Radio Coexistence

Volume 57-II, Issue 7

497 -- 501Jeffrey S. Walling, David J. Allstot. Linearizing CMOS Switching Power Amplifiers Using Supply Regulators
502 -- 506Young-Kyun Cho, Young-Deuk Jeon, Jae-Won Nam, Jong-Kee Kwon. A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique
507 -- 511Tejinder Singh Sandhu, Kamal El-Sankary, Ezz I. El-Masry. A Distortion-Compensated Charge Transfer Amplifier for a 1.66-MHz Cyclic Pipeline ADC
512 -- 516Heather Orser, Anand Gopinath. A 20 GS/s 1.2 V 0.13 muhboxm CMOS Switched Cascode Track-and-Hold Amplifier
517 -- 521Min C. Park, Michael H. Perrott, Robert Bogdan Staszewski. A Time-Domain Resolution Improvement of an RF-DAC
522 -- 526Chin-Lung Yang, Shin-Yi Shu, Yi-Chyun Chiang. Design of a K-Band Chip Filter With Three Tunable Transmission Zeros Using a Standard 0.13-muhboxm CMOS Technology
527 -- 530Toru Tanzawa. A Behavior Model of a Dickson Charge Pump Circuit for Designing a Multiple Charge Pump System Distributed in LSIs
531 -- 535Alex K. Y. Wong, Ka Nang Leung, Kong-Pang Pun, Yuan-Ting Zhang. A 0.5-Hz High-Pass Cutoff Dual-Loop Transimpedance Amplifier for Wearable NIR Sensing Device
536 -- 540Chih-Jung Chen, Tah-Hsiung Chu, Chih-Lung Lin, Zeui-Chown Jou. A Study of Loosely Coupled Coils for Wireless Power Transfer
541 -- 545Rajeev K. Dokania, Xiao Wang, Siddharth G. Tallur, Carlos I. Dorta-Quinones, Alyssa B. Apsel. An Ultralow-Power Dual-Band UWB Impulse Radio
546 -- 550Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee. A Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators
551 -- 555Honggang Qi, Qingming Huang, Wen Gao. A Low-Cost Very Large Scale Integration Architecture for Multistandard Inverse Transform
556 -- 560Won Namgoong. Flicker Noise in Observer-Controller Digital PLL
561 -- 565Hyunbean Yi, Sandip Kundu, Sangwook Cho, Sungju Park. A Scan Cell Design for Scan-Based Debugging of an SoC With Multiple Clock Domains
566 -- 570Cheng-Chi Wong, Hsie-Chia Chang. Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System
571 -- 575Sheau-Fang Lei, Shin-Chi Lai, Po-Yin Cheng, Ching-Hsing Luo. Low Complexity and Fast Computation for Recursive MDCT and IMDCT Algorithms

Volume 57-II, Issue 6

405 -- 410Gabor C. Temes. Micropower Data Converters: A Tutorial
411 -- 415Sungho Lee, Sangwook Nam. A CMOS Outphasing Power Amplifier With Integrated Single-Ended Chireix Combiner
416 -- 420Bart De Vuyst, Pieter Rombouts, Jeroen De Maeyer, Georges G. E. Gielen. The Nyquist Criterion: A Useful Tool for the Robust Design of Continuous-Time SigmaDelta Modulators
421 -- 425Lei Wang, Leibo Liu, Hongyi Chen. An Implementation of Fast-Locking and Wide-Range 11-bit Reversible SAR DLL
426 -- 429Hannu Olkkonen, Juuso T. Olkkonen. Sampling and Reconstruction of Transient Signals by Parallel Exponential Filters
430 -- 434Chia-Tsun Wu, Wen-Chung Shen, Wei Wang, An-Yeu Wu. A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm
435 -- 439Jong-Min Baek, Jung-Hoon Chun, Kee-Won Kwon. A Power-Efficient Voltage Upconverter for Embedded EEPROM Application
440 -- 445Shien-Chun Luo, Lih-Yih Chiou. A Sub-200-mV Voltage-Scalable SRAM With Tolerance of Access Failure by Self-Activated Bitline Sensing
446 -- 450Dragana Prokin, Milan Prokin. Low Hardware Complexity Pipelined Rank Filter
451 -- 455Song-Nien Tang, Jui-Wei Tsai, Tsin-Yuan Chang. A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications
456 -- 460Du-Qu Wei, Bo Zhang, Dong Yuan Qiu, Xiao-Shu Luo. Effects of Current Time-Delayed Feedback on the Dynamics of a Permanent-Magnet Synchronous Motor
461 -- 465Zongbo Xie, Jiuchao Feng. Blind Source Separation of Continuous-Time Chaotic Signals Based on Fast Random Search Algorithm
466 -- 470Andrzej Borys. Consideration of Volterra Series With Excitation and/or Impulse Responses in the Form of Dirac Impulses
471 -- 475François Auger. Some New Developments on the Al-Alaoui and the Pei and Hsu s-to-z Transforms
476 -- 480Wutao Yin, Aryan Saadat Mehr. A Variable Regularization Method for Affine Projection Algorithm
481 -- 485G. P. Liu. Predictive Controller Design of Networked Systems With Communication Delays and Data Loss
486 -- 490Yanbo Gao, Guoping Lu, Zhiming Wang. Passivity Analysis of Uncertain Singularly Perturbed Systems

Volume 57-II, Issue 5

317 -- 318Vladimir Stojanovic, Chih-Kong Ken Yang, Ron Ho. Guest Editorial for Special Issue on High-Performance Multichip Interconnections
319 -- 323Shih-Yuan Kao, Shen-Iuan Liu. A 20-Gb/s Transmitter With Adaptive Preemphasis in 65-nm CMOS Technology
324 -- 328Kuo-Hsing Cheng, Yu-Chang Tsai, Yen-Hsueh Wu, Ying-Fu Lin. A 5-Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications
329 -- 333Ahmed Nassar, Ahmed Emira, Ahmed Nader Mohieldin, Ahmed Hussien Khalil. Multichannel Clock and Data Recovery: A Synchronous Approach
334 -- 338Jaejun Lee, Sungho Lee, Sangwook Nam. Multi-Slot Main Memory System for Post DDR3
339 -- 342Farshid Aryanfar, Amir Amirkhany. A Low-Cost Resonance Mitigation Technique for Multidrop Memory Interfaces
343 -- 347Arun Palaniappan, Samuel Palermo. Power Efficiency Comparisons of Interchip Optical Interconnect Architectures
348 -- 352Jung-Won Han, Boo-Young Choi, Mikyung Seo, Jisook Yun, Dongmyung Lee, Taewook Kim, YunSeong Eo, Sung Min Park. A 20-Gb/s Transformer-Based Current-Mode Optical Receiver in 0.13-μm CMOS
353 -- 358Won Namgoong, Lei Feng. Digital Processing of Single-Carrier Cyclic Prefixed Frequency Channelized Receiver for Serial Links
359 -- 363Rajan Narasimha, Naresh R. Shanbhag. Design of Energy-Efficient High-Speed Links via Forward Error Correction
364 -- 368Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli. Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands
369 -- 373Meng-Hung Shen, Jen-Huan Tsai, Po-Chiun Huang. Random Swapping Dynamic Element Matching Technique for Glitch Energy Minimization in Current-Steering DAC
374 -- 378Lucas Andrew Milner, Gabriel A. Rincón-Mora. A Feedforward 10times CMOS Current-Ripple Suppressor for Switching Power Supplies
379 -- 383Young Hun Seo, Young Sang Kim, Hong June Park, Jae-Yoon Sim. A 5 Gb/s Transmitter With a TDR-Based Self-Calibration of Preemphasis Strength
384 -- 388Qiang Zhu, Yang Xu. Quadrature Sampling for Built-In Analog/RF IC Spectrum Test
389 -- 393Karun Rawat, Meenakshi Rawat, Fadhel M. Ghannouchi. Compensating I-Q Imperfections in Hybrid RF/Digital Predistortion With an Adapted Lookup Table Implemented in an FPGA
394 -- 398Roger Yubtzuan Chen, Zong-Yi Yang. Modeling the High-Frequency Degradation of Phase/Frequency Detectors
399 -- 403Bo Fu, Paul Ampadu. Exploiting Parity Computation Latency for On-Chip Crosstalk Reduction

Volume 57-II, Issue 4

245 -- 249Socheat Heng, Cong-Kha Pham. A Low-Power High-PSRR Low-Dropout Regulator With Bulk-Gate Controlled Circuit
250 -- 254Annajirao Garimella, M. Wasequr Rashid, Paul M. Furth. Reverse Nested Miller Compensation Using Current Buffers in a Three-Stage LDO
255 -- 259Chi-En Liu, Yi-Jhan Hsieh, Jean-Fu Kiang. RFID Regulator Design Insensitive to Supply Voltage Ripple and Temperature Variation
260 -- 264Mehdi Kiani, Maysam Ghovanloo. An RFID-Based Closed-Loop Wireless Power Transmission System for Biomedical Applications
265 -- 269Chua-Chin Wang, Chih-Lin Chen, Ron-Chi Kuo, Doron Shmilovitz. Self-Sampled All-MOS ASK Demodulator for Lower ISM Band Applications
270 -- 274Nitesh Singhal, Sudhakar Pamarti. A Digital Envelope Combiner for Switching Power Amplifier Linearization
275 -- 279Gordana Jovanovic-Dolecek, Massimiliano Laddomada. An Economical Class of Droop-Compensated Generalized Comb Filters: Analysis and Design
280 -- 284Gabriel Torrens, Bartomeu Alorda, Salvador Barcelo, José Luis Rosselló, Sebastiàn A. Bota, Jaume Segura. Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination
285 -- 289Pramod Kumar Meher. LUT Optimization for Memory-Based Computation
290 -- 294Stuart N. Wooters, Benton H. Calhoun, Travis N. Blalock. An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS
295 -- 299Alexandru Amaricai, Mircea Vladutiu, Oana Boncalo. Design Issues and Implementations for Floating-Point Divide-Add Fused
300 -- 304Xi Chen, Siu Chung Wong, Chi Kong Tse. Adding Randomness to Modeling Internet TCP-RED Systems With Interactive Gateways
305 -- 309Alexander Jimenez Triana, Wallace Kit-Sang Tang, Guanrong Chen, Alain Gauthier. Chaos Control in Duffing System Using Impulsive Parametric Perturbations
310 -- 314Rui Wang, Bo Wang, Guo-Ping Liu, Wei Wang 0036, David Rees. infty Controller Design for Networked Predictive Control Systems Based on the Average Dwell-Time Approach

Volume 57-II, Issue 3

153 -- 157Gordon W. Roberts, Mohammed Ali-Bakhshian. A Brief Introduction to Time-to-Digital and Digital-to-Time Converters
158 -- 162Shanthi Pavan. Systematic Design Centering of Continuous Time Oversampling Converters
163 -- 167Jin-Fu Lin, Soon-Jyh Chang, Chun-Cheng Liu, Chih-Hao Huang. A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS Technique
168 -- 172Chun-Hsien Kuo, Tai-Haur Kuo, Kow-Liang Wen. Bias-and-Input Interchanging Technique for Cyclic/Pipelined ADCs With Opamp Sharing
173 -- 177Jaemo Yang, Choul-Young Kim, Dong Wook Kim, Songcheol Hong. Design of a 24-GHz CMOS VCO With an Asymmetric-Width Transformer
178 -- 182Shih-Yuan Kao, Shen-Iuan Liu. A 1.62/2.7-Gb/s Adaptive Transmitter With Two-Tap Preemphasis Using a Propagation-Time Detector
183 -- 187Pavel Poliakov, Ankur Anchlia, Marie Garcia Bardon, Bram Rooseleer, Bart De Wachter, Nadine Collaert, Koen van der Zanden, Wim Dehaene, Diederik Verkest, Miguel Corbalan Miranda. Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM
188 -- 192Taejoong Song, Jongmin Park, Sang Min Lee, Jaehyouk Choi, Kihong Kim, Chang-Ho Lee, Kyutae Lim, Joy Laskar. A 122-mW Low-Power Multiresolution Spectrum-Sensing IC With Self-Deactivated Partial Swing Techniques
193 -- 197Jaimin Mehta, Vasile Zoicas, Oren Eliezer, Robert Bogdan Staszewski, Sameh Rezeq, Mitch Entezari, Poras T. Balsara. An Efficient Linearization Scheme for a Digital Polar EDGE Transmitter
198 -- 202Tso-Bing Juang, Chin-Chieh Chiu, Ming-Yu Tsai. n + 1 Adder Design With Simple Correction Schemes
203 -- 207Raj S. Katti, Rajesh G. Kavasseri, Vyasa Sai. Pseudorandom Bit Generation Using Coupled Congruential Generators
208 -- 212Subho Chatterjee, Sayeef Salahuddin, Saibal Mukhopadhyay. Dual-Source-Line-Bias Scheme to Improve the Read Margin and Sensing Accuracy of STTRAM in Sub-90-nm Nodes
213 -- 217Antonio Loría. Master-Slave Synchronization of Fourth-Order Lü Chaotic Oscillators via Linear Output Feedback
218 -- 222Abdelali El Aroudi, Enric Rodriguez, Ramon Leyva, Eduard Alarcón. A Design-Oriented Combined Approach for Bifurcation Prediction in Switched-Mode Power Converters
223 -- 227Ricardo Riaza. Nondegeneracy Conditions for Active Memristive Circuits
228 -- 232Hye-Yoon Joo, Lee-Sup Kim. A Data-Pattern-Tolerant Adaptive Equalizer Using the Spectrum Balancing Method
233 -- 237Liang Li, Robert G. Maunder, Bashir M. Al-Hashimi, Lajos Hanzo. An Energy-Efficient Error Correction Scheme for IEEE 802.15.4 Wireless Sensor Networks
238 -- 242Hoi Lee, Seong-Ryong Ryu. An Efficiency-Enhanced DCM Buck Regulator With Improved Switching Timing of Power Transistors

Volume 57-II, Issue 2

69 -- 74Ian Galton. Why Dynamic-Element-Matching DACs Work
75 -- 79Jean-Michel Redoute, Michiel Steyaert. Kuijk Bandgap Voltage Reference With High Immunity to EMI
80 -- 84Edward N. Y. Ho, Philip K. T. Mok. A Capacitor-Less CMOS Active Feedback Low-Dropout Regulator With Slew-Rate Enhancement for Portable On-Chip Application
85 -- 89Hyunchol Shin, Youngcho Kim. RC Low-Pass Filter With Simultaneously Tunable High- and Low-Cutoff Frequencies for IEEE 802.22 Applications
90 -- 94Zhenbiao Li, Ming Li, Dong Zhao, Dequn Ma, Wenhai Ni, Zhongming Ouyang. TD-SCDMA/HSDPA Transceiver and Analog Baseband Chipset in 0.18-μm CMOS Process
95 -- 99Alexander Vaz, Aritz Ubarretxena, Ibon Zalbide, Daniel Pardo, Héctor Solar, Andrés Garcia-Alonso, Roc Berenguer. Full Passive UHF Tag With a Temperature Sensor Suitable for Human Body Temperature Monitoring
100 -- 104Nathan Schemm, Sina Balkir, Michael W. Hoffman. A 4-muhboxW CMOS Front End for Particle Detection Applications
105 -- 109João P. Oliveira, João Goes, Michael Figueiredo, Edinei Santin, João Fernandes, J. Ferreira. An 8-bit 120-MS/s Interleaved CMOS Pipeline ADC Based on MOS Parametric Amplification
110 -- 114Junjie Yao, Jin Liu, Hoi Lee. Bulk Voltage Trimming Offset Calibration for High-Speed Flash ADCs
115 -- 119Marko Neitola, Timo Rahkonen. A Generalized Data-Weighted Averaging Algorithm
120 -- 125Young-Ho Kwak, Inhwa Jung, Chulwoo Kim. A Gb/s+ Slew-Rate/Impedance-Controlled Output Driver With Single-Cycle Compensation Time
126 -- 130Chi-Chun Huang, Tzung-Je Lee, Wei-Chih Chang, Chua-Chin Wang. (1/3) times hboxVDD-to- (3/2) times hboxVDD Wide-Range I/O Buffer Using 0.35- muhboxm 3.3-V CMOS Technology
131 -- 135Tomaso Poggi, Francesco Comaschi, Marco Storace. Digital Circuit Realization of Piecewise-Affine Functions With Nonuniform Resolution: Theory and FPGA Implementation
136 -- 140Chao-Ming Chen, Chien-Chang Hung, Yuan-Hao Huang. An Energy-Efficient Partial FFT Processor for the OFDMA Communication System
141 -- 145Jun Sun, Wei Fang, Wenbo Xu. A Quantum-Behaved Particle Swarm Optimization With Diversity-Guided Mutation for the Design of Two-Dimensional IIR Digital Filters
146 -- 150Kwok-Wo Wong, Qiuzhen Lin, Jianyong Chen. Simultaneous Arithmetic Coding and Encryption Using Chaotic Maps

Volume 57-II, Issue 12

921 -- 925Ehab Ahmed Sobhy, Sebastian Hoyos. A Multiphase Multipath Technique With Digital Phase Shifters for Harmonic Distortion Cancellation
926 -- 930Omeed Momeni, Hossein Hashemi, Ehsan Afshari. A 10-Gb/s Inductorless Transimpedance Amplifier
931 -- 935Gary J. Ballantyne, Jifeng Geng. Effect of Reference Clock Jitter and Demonstration of Near Image-Free Operation for the ADPLL
936 -- 940Wu-Hsin Chen, Maciej E. Inerowicz, Byunghoo Jung. Phase Frequency Detector With Minimal Blind Zone for Fast Frequency Acquisition
941 -- 945Stefan Tertinek, James P. Gleeson, Orla Feely. Binary Phase Detector Gain in Bang-Bang Phase-Locked Loops With DCO Jitter
946 -- 950Fang-Ren Liao, Shey-Shi Lu. A Programmable Edge-Combining DLL With a Current-Splitting Charge Pump for Spur Suppression
951 -- 955Shu-Yu Hsu, Jui-Yuan Yu, Chen-Yi Lee. A Sub-10-muhboxW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications
956 -- 960Shunsuke Okura, Hajime Shibata, Tetsuro Okura, Toru Ido, Kenji Taniguchi 0001. A Frequency Model of a Continuously Driven Clocked CMOS Comparator
961 -- 965Bei Peng, Hao Li 0001, Pingfen Lin, Yun Chiu. An Offset Double Conversion Technique for Digital Calibration of Pipelined ADCs
966 -- 970Mohamed Aboudina, Behzad Razavi. A New DAC Mismatch Shaping Technique for Sigma-Delta Modulators
971 -- 974Alaa I. Abunjaileh, Ian C. Hunter. Direct Synthesis of Parallel-Connected Symmetrical Two-Port Filters
975 -- 979Ivo Petras. Fractional-Order Memristor-Based Chua's Circuit
980 -- 985Meng-Fan Chang, Yung-Chi Chen, Chien-Fu Chen. A 0.45-V 300-MHz 10T Flowthrough SRAM With Expanded write/ read Stability and Speed-Area-Wise Array for Sub-0.5-V Chips
986 -- 990Sangho Shin, Kyungmin Kim, Sung-Mo Kang. Data-Dependent Statistical Memory Model for Passive Array of Memristive Devices
991 -- 995Mariano Fons, Francisco Fons, Enrique Cantó. Fingerprint Image Processing Acceleration Through Run-Time Reconfigurable Hardware
996 -- 1000Shih-Liang Chen, TingTing Hwang, Wen-Wei Lin. Randomness Enhancement Using Digitalized Modified Logistic Map
1001 -- 1005Shilian Wang, Xiaodong Wang. M-DCSK-Based Chaotic Communications in MIMO Multipath Channels With No Channel State Information

Volume 57-II, Issue 11

833 -- 837Paschalis Simitsakis, Yannis Papananos, Eleni-Sotiria Kytonaki. Design of a Low Voltage-Low Power 3.1-10.6 GHz UWB RF Front-End in a CMOS 65 nm Technology
838 -- 842Javad Javidan, Mojtaba Atarodi, Howard C. Luong. High Power Amplifier Based on a Transformer-Type Power Combiner in CMOS Technology
843 -- 847Shuenn-Yuh Lee, Liang-Hung Wang, Yu-Heng Lin. A CMOS Quadrature VCO With Subharmonic and Injection-Locked Techniques
848 -- 852Joseph Hamilton, Shouli Yan, T. R. Viswanathan. A Discrete-Time Input Delta Sigma ADC Architecture Using a Dual-VCO-Based Integrator
853 -- 857Bei Peng, Hao Li 0001, Seung-Chul Lee, Pingfen Lin, Yun Chiu. A Virtual-ADC Digital Background Calibration Technique for Multistage A/D Conversion
858 -- 862Marko Neitola, Timo Rahkonen, Janne Raappana. A Qualification Approach to DAC Mismatch-Shaping Methods
863 -- 867Juan M. Carrillo, Guido Torelli, Miguel Angel Domínguez, Raquel Pérez-Aloe, José M. Valverde, J. Francisco Duque-Carrillo. A Family of Low-Voltage Bulk-Driven CMOS Continuous-Time CMFB Circuits
868 -- 873Amit P. Patel, Gabriel A. Rincón-Mora. High Power-Supply-Rejection (PSR) Current-Mode Low-Dropout (LDO) Regulator
874 -- 877Hung-Yu Wang, Wen-Chung Huang, Nan-Hui Chiang. Symbolic Nodal Analysis of Circuits Using Pathological Elements
878 -- 882Bongsub Song, Nayeon Cho, Byunghoon Kim, Jung Han Choi, Young-Lok Kim, Jinwook Burm. An Autofocus Sensor With Global Shutter Using Offset-Free Frame Memory
883 -- 887Ahmed Shahein, Mohamed Afifi, Markus Becker, Niklas Lotze, Yiannos Manoli. A Power-Efficient Tunable Narrow-Band Digital Front End for Bandpass Sigma-Delta ADCs in Digital FM Receivers
888 -- 892Yen-Jen Chang. Using the Dynamic Power Source Technique to Reduce TCAM Leakage Power
893 -- 897Kevin Cushon, Camille Leroux, Saied Hemati, Shie Mannor, Warren J. Gross. A Min-Sum Iterative Decoder Based on Pulsewidth Message Encoding
898 -- 902Ming Li, Chi Kong Tse, Herbert H. C. Iu, Xikui Ma. Unified Equivalent Modeling for Stability Analysis of Parallel-Connected DC/DC Converters
903 -- 907Phatiphat Thounthong, Serge Pierfederici. A New Control Law Based on the Differential Flatness Principle for Multiphase Interleaved DC-DC Converter
908 -- 912Bor-Ren Lin, Yu-Siang Huang. ZVS Double-Ended Ćuk Converter
913 -- 917Yun-Bo Zhao, Guo-Ping Liu, David Rees. Actively Compensating for Data Packet Disorder in Networked Control Systems

Volume 57-II, Issue 10

757 -- 761Pui Ying Or, Ka Nang Leung. A Fast-Transient Low-Dropout Regulator With Load-Tracking Impedance Adjustment and Loop-Gain Boosting Technique
762 -- 766Indika U. K. Bogoda Appuhamylage, Shunsuke Okura, Toru Ido, Kenji Taniguchi 0001. An Area-Efficient CMOS Bandgap Reference Utilizing a Switched-Current Technique
767 -- 771Xin-ming, Ying-qian Ma, Ze-kun Zhou, Bo Zhang. A High-Precision Compensated CMOS Bandgap Voltage Reference Without Resistors
772 -- 776Michael Margaliot, George Weiss. The Low-Frequency Distortion in D-Class Amplifiers
777 -- 781Stanislaw J. Piestrak, Sébastien Pillement, Olivier Sentieys. Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication
782 -- 786Xiaoheng Chen, Shu Lin, Venkatesh Akella. QSN - A Simple Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders
787 -- 792Xinmiao Zhang, Jiangli Zhu. Algebraic Soft-Decision Decoder Architectures for Long Reed-Solomon Codes
793 -- 797Golnar Khodabandehloo, Mitra Mirhassani, Majid Ahmadi. Resistive-Type CVNS Distributed Neural Networks With Improved Noise-to-Signal Ratio
798 -- 802Kyung Ki Kim, Wei Wang 0029, Ken Choi. On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits
803 -- 807Simin Yu, Jinhu Lu, Guanrong Chen, Xinghuo Yu. Design and Implementation of Grid Multiwing Butterfly Chaotic Attractors From a Piecewise Lorenz System
808 -- 812Erick O. Torres, Gabriel A. Rincón-Mora. Self-Tuning Electrostatic Energy-Harvester IC
813 -- 817Chia-Ling Wei, Chun-Hsien Wu, Lu-Yao Wu, Ming-Hsien Shih. An Integrated Step-Up/Step-Down DC-DC Converter Implemented With Switched-Capacitor Circuits
818 -- 822Mohammad A. Al-Shyoukh, Hoi Lee. A Compact Fully-Integrated Extremum-Selector-Based Soft-Start Circuit for Voltage Regulators in Bulk CMOS Technologies
823 -- 827Ching-Tsai Pan, Ching-Ming Lai, Yu-Lin Juan. Output Current Ripple-Free PWM Inverters
828 -- 832Guoyong Shi. Computational Complexity Analysis of Determinant Decision Diagram

Volume 57-II, Issue 1

1 -- 5Ping Gui, Zheng Gao, Chen-Wei Huang, Liming Xiu. The Effects of Flying-Adder Clocks on Digital-to-Analog Converters
6 -- 10Mohamed Helaoui, Fadhel M. Ghannouchi. Linearization of Power Amplifiers Using the Reverse MM-LINC Technique
11 -- 15Mu-Chen Huang, Shen-Iuan Liu. A 10-MS/s-to-100-kS/s Power-Scalable Fully Differential CBSC 10-Bit Pipelined ADC With Adaptive Biasing
16 -- 20He Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins. A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS
21 -- 25Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen. Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment
26 -- 30Chen-Fong Hsiao, Yuan Chen, Chen-Yi Lee. A Generalized Mixed-Radix Algorithm for Memory-Based FFT Processors
31 -- 35Chua-Chin Wang, Chia-Hao Hsu, Chi-Chun Huang, Jun-Han Wu. A Self-Disabled Sensing Technique for Content-Addressable Memories
36 -- 40He Huang, Gang Feng. A Scaling Parameter Approach to Delay-Dependent State Estimation of Delayed Neural Networks
41 -- 45Chengde Zheng, Huaguang Zhang, Zhanshan Wang. Improved Robust Stability Criteria for Delayed Cellular Neural Networks via the LMI Approach
46 -- 50Maoyin Chen. Synchronization in Complex Dynamical Networks With Random Sensor Delay
51 -- 55Jun Lin, Jin Sha, Zhongfeng Wang, Li Li 0003. An Efficient VLSI Architecture for Nonbinary LDPC Decoders
56 -- 60Abdelali El Aroudi, Mohamed Orabi. Stabilizing Technique for AC-DC Boost PFC Converter Based on Time Delay Feedback
61 -- 65Zheng Zhang, Ngai Wong. Passivity Test of Immittance Descriptor Systems Based on Generalized Hamiltonian Methods