Journal: IEEE Trans. Circuits Syst. II Express Briefs

Volume 50, Issue 9

497 -- 517Andre Tkacenko, P. P. Vaidyanathan, T. Q. Nguyen. On the eigenfilter design method and its applications: a tutorial
518 -- 530Omid Oliaei. Sigma-delta modulator with spectrally shaped feedback
531 -- 538Jipeng Li, Un-Ku Moon. Background calibration techniques for multistage pipelined ADCs with digital redundancy
539 -- 552Anthony Chan Carusone, D. A. Johns. Digital LMS adaptation of analog filters without gradient information
553 -- 566Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu, Ding-Ming Kwai. Practical considerations in applying /spl Sigma/-/spl Delta/ modulation-based analog BIST to sampled-data systems
567 -- 578J. M. Pierre Langlois, Dhamin Al-Khalili. Novel approach to the design of direct digital frequency synthesizers based on linear interpolation
579 -- 588A. C. H. MeVay, R. Sarpeshkar. Predictive comparators with adaptive control
589 -- 601Cheng-Shing Wu, An-Yeu Wu, Chih-Hsiu Lin. A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes
602 -- 614Yuanjin Zheng, Zhiping Lin. Recursive adaptive algorithms for fast and rapidly time-varying systems
615 -- 626Liqian Zhang, Biao Huang, James Lam. LMI synthesis of H/sub 2/ and mixed H/sub 2//H/sub /spl infin// controllers for singular systems
627 -- 631K. Ishida, M. Fujishima. Chopper-stabilized high-pass sigma delta modulator utilizing a resonator structure
631 -- 634Ahmed M. A. Ali, K. Nagaraj. Background calibration of operational amplifier gain error in pipelined A/D converters
634 -- 640Shahin Jafarabadi-Ashtiani, Omid Shoaei, S. M. Rezaul Hasan, Azam Jannesari. On the parasitic-sensitivity of switched-capacitor summing-integrator structures for /spl Sigma//spl Delta/ modulators
641 -- 648Kong-Pang Pun, José E. da Franca, Carlos Azeredo Leme, Ricardo Reis 0001. Quadrature sampling schemes with improved image rejection
649 -- 653Apisak Worapishet, John B. Hughes, Christofer Toumazou. Low-power high-frequency class-AB two-step sampling switched-current techniques
653 -- 656Chien-Cheng Tseng. Design of IIR digital all-pass filters using least pth phase error criterion
657 -- 659Dean J. Schmidlin. Modeling of fractional-order signals from their ramp cepstra
659 -- 662Yang Shi 0001, Tongwen Chen. Optimal design of multichannel transmultiplexers with stopband energy and passband magnitude constraints
662 -- 666Krzysztof Galkowski, Wojciech Paszke, Eric Rogers, Shengyuan Xu, James Lam, David H. Owens 0001. Stability and control of differential linear repetitive processes using an LMI setting
666 -- 669Li Xu 0004, Jiang Qian Ying, Zhiping Lin, Osami Saito. Comments on "Stability tests of N-dimensional discrete time systems using polynomial arrays

Volume 50, Issue 8

397 -- 403L. Lentola, A. Mozzi, A. Neviani, Andrea Baschirotto. A 1-/spl mu/A front end for pacemaker atrial sensing channels with early sensing capability
404 -- 414José L. Ausín, J. Francisco Duque-Carrillo, Guido Torelli, Edgar Sánchez-Sinencio. Switched-capacitor circuits with periodical nonuniform individual sampling
415 -- 423Hengsheng Liu, Aydin I. Karsilayan. An accurate automatic tuning scheme for high-Q continuous-time bandpass filters based on amplitude comparison
424 -- 436Hui Pan, Asad A. Abidi. Spatial filtering in flash A/D converters
437 -- 444Omid Oliaei. Design of continuous-time sigma-delta modulators with arbitrary feedback waveform
445 -- 449Ka-Wai Ho, H. C. Luong. A 1-V CMOS power amplifier for Bluetooth applications
450 -- 455Joseph M. C. Wong, H. C. Luong. A 1.5-V 4-GHz dynamic-loading regenerative frequency doubler in a 0.35-/spl mu/m CMOS process
456 -- 469Shahriar Mirabbasi, Ken Martin. Overlapped complex-modulated transmultiplexer filters with simplified design and superior stopbands
470 -- 480Tian-Bo Deng, Eiji Okamoto. SVD-based design of fractional-delay 2-D digital filters exploiting specification symmetries
481 -- 484Alexandru A. Ciubotaru. Absolute-value circuit using junction field-effect transistors
484 -- 487Romano Fantacci, Mauro Forti, Mauro Marini, Daniele Tarchi, Gianluca Vannuccini. A neural network for constrained optimization with application to CDMA communication systems
488 -- 493Giovanni Dimauro, Sebastiano Impedovo, Raffaele Modugno, Giuseppe Pirlo, R. Stefanelli. Residue-to-binary conversion by the "quotient function"
493 -- 0Sunder S. Kidambi. Comments on "2-D FIR filters design using least square error with scaling-free McClellan transformation"

Volume 50, Issue 7

329 -- 342Tina A. Hudson, Julian A. Bragg, Paul E. Hasler, Stephen P. DeWeerth. An analog VLSI model of muscular contraction
343 -- 354Juha Häkkinen, Juha Kostamovaara. Speeding up an integer-N PLL by controlling the loop filter charge
355 -- 367Per Löwenborg, Håkan Johansson, Lars Wanhammar. Two-channel digital and hybrid analog/digital multirate filter banks with very low-complexity analysis or synthesis filters
368 -- 375Saman S. Abeysekera, Xue Yao, Charoensak Charayaphan. Design of optimal and narrow-band Laguerre filters for sigma-delta demodulators
376 -- 378Eduard F. Stikvoort. Polyphase filter section with opamps
378 -- 383Haijiang Ou, K. K. Chin. Theory of gated multicycle integration (GMCI) for repetitive imaging of focal plane array
383 -- 389Roberto López-Valcarce, Fernando Pérez-González. Subband hyperstable adaptive IIR filters
389 -- 392Beth Wilson, Magdy A. Bayoumi. A computational kernel for fast and efficient compressed-domain calculations of wavelet subband energies

Volume 50, Issue 6

257 -- 266Yong Ching Lim, Ya Jun Yu. A width-recursive depth-first tree search approach for the design of discrete coefficient perfect reconstruction lattice filter bank
267 -- 277Tian-Bo Deng. Design of linear-phase variable 2-D digital filters using matrix-array decomposition
278 -- 287Hussain A. Alzaher, Hassan O. Elwan, Mohammed Ismail 0001. A CMOS fully balanced second-generation current conveyor
288 -- 298Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Toshifumi Watanabe, Tadahiro Ohmi. Extraction of instantaneous and RMS sinusoidal jitter using an analytic signal method
299 -- 314Xin Li 0001, Xuan Zeng 0001, Dian Zhou, Xieting Ling, Wei Cai 0003. Behavioral modeling for analog system-level simulation by wavelet collocation method
315 -- 317M. Keskin. A novel low-voltage switched-capacitor input branch
317 -- 322Javier Valls, Eduardo I. Boemo. Efficient FPGA-implementation of two's complement digit-serial/parallel multipliers
322 -- 325Yun-Nan Chang, Keshab K. Parhi. An efficient pipelined FFT architecture
325 -- 0Costas Psychalinos, Spyridon Vlassis. On the exact realization of log-domain elliptic filters using the signal flow graph approach

Volume 50, Issue 5

205 -- 213Michael P. Flynn, C. Donovan, L. Sattler. Digital calibration incorporating redundancy of flash ADCs
214 -- 220Jaime Ramírez-Angulo, Carlos Urquidi, Ramón González Carvajal, Antonio Torralba 0002, Antonio J. López-Martín. A new family of very low-voltage analog circuits based on quasi-floating-gate transistors
221 -- 227T. K. Pham, P. E. Allen. A highly accurate step-response-based successive-approximation frequency tuning scheme for high-Q continuous-time bandpass filters
227 -- 233Rosario Mita, Gaetano Palumbo, Salvatore Pennisi. Design guidelines for reversed nested Miller compensation in three-stage amplifiers
234 -- 238Nguyen T. Thao. Asymptotic MSE law of nth-order /spl Sigma//spl Delta/ modulators
238 -- 243Yeun-Ting Fong, Chi-Wah Kok. Iterative least squares design of DC-leakage free paraunitary cosine modulated filter banks
243 -- 250Tian-Bo Deng. Design and parallel implementation of FIR digital filters with simultaneously variable magnitude and non-integer phase-delay
250 -- 254Antonio G. M. Strollo, Davide De Caro. Booth folding encoding for high performance squarer circuits

Volume 50, Issue 4

157 -- 163Pieter Rombouts, Johan Raman, Ludo Weyten. An approach to tackle quantization noise folding in double-sampling /spl Sigma//spl Delta/ modulation A/D converters
164 -- 169Håkan Johansson, Per Löwenborg. On the design of adjustable fractional delay FIR filters
169 -- 175Zhaohui Liu, John V. McCanny, Gaye Lightbody, Richard L. Walke. Generic SoC QR array processor for adaptive beamforming
176 -- 180Thomas Riley, Juha Kostamovaara. A hybrid /spl Delta//spl Sigma/ fractional-N frequency synthesizer
181 -- 186H. Kulah, T. Akin. A current mirroring integration based readout circuit for high performance infrared FPA applications
187 -- 190Rosario Mita, Gaetano Palumbo, Salvatore Pennisi. 1.5-V CMOS CCII+ with high current-driving capability
191 -- 195Jader A. De Lima, Adriano S. Cordeiro. A low-voltage low-power analog memory cell with built-in 4-quadrant multiplication
195 -- 202S. Fiori. Extended Hebbian learning for blind separation of complex-valued sources

Volume 50, Issue 3

105 -- 117Saska Lindfors, Aarno Pärssinen, Kari A. I. Halonen. A 3-V 230-MHz CMOS decimation subsampler
118 -- 129Aria Eshraghi, Terri S. Fiez. A time-interleaved parallel /spl Delta//spl Sigma/ A/D converter
130 -- 134Liming Xiu, Zhihong You. A new frequency synthesis method based on "flying-adder" architecture
135 -- 138Francisco Cardells-Tormo, Javier Valls-Coquillat. Area-optimized implementation of quadrature direct digital frequency synthesizers on LUT-based FPGAs
139 -- 143Zidong Wang, Xiaohui Liu. On designing H/sub /spl infin// filters with circular pole and error variance constraints
143 -- 149Min Li, Chi-Wah Kok. Linear phase filter bank design using LMI-based H/sub /spl infin// optimization
150 -- 154Dusan Veselinovic, Daniel Graupe. A wavelet transform approach to blind adaptive filtering of speech from unknown noises

Volume 50, Issue 2

53 -- 62A. M. Fahim, Mohamed I. Elmasry. A wideband sigma-delta phase-locked-loop modulator for wireless applications
63 -- 72A. M. Fahim, Mohamed I. Elmasry. A fast lock digital phase-locked-loop architecture for wireless applications
73 -- 82Sung-Won Lee, In-Cheol Park. A low-power variable length decoder for MPEG-2 based on successive decoding of short codewords
83 -- 93Jinwen Zan, M. Omair Ahmad, M. N. S. Swamy. Pyramidal motion estimation techniques exploiting intra-level motion correlation
93 -- 101Corneliu Rusu, Pauli Kuosmanen. Phase approximation by logarithmic sampling of gain

Volume 50, Issue 12

905 -- 0Ian Galton. Editorial
906 -- 917Ojas Choksi, L. Richard Carley. Analysis of switched-capacitor common-mode feedback circuit
918 -- 927Carlos Aristoteles De la Cruz-Blas, Antonio J. López-Martín, Alfonso Carlosena. 1.5-V MOS translinear loops with improved dynamic range and their applications to current-mode signal processing
928 -- 932Rasoul Dehghani, Seyed Mojtaba Atarodi. A new low voltage precision CMOS current reference with no external components
933 -- 941P. K. Chan, Y.-C. Chen. Gain-enhanced feedforward path compensation technique for pole-zero cancellation at heavy capacitive loads
942 -- 949Yue Wu, Xiaohui Ding, Mohammed Ismail 0001, Håkan Olsson. RF bandpass filter design based on CMOS active inductors
950 -- 962Brent Buchanan, Martin A. Brooke. An experimental evaluation of error spectrum shaping applied to mixed-signal image convolutions
963 -- 976Ying-Jui Chen, Kevin Amaratunga. M-channel lifting factorization of perfect reconstruction filter banks and reversible M-band wavelet transforms
977 -- 983Kazuyoshi Uesaka, Masayuki Kawamata. Evolutionary synthesis of digital filter structures using genetic programming
984 -- 993Sang-Min Kim, Jin-Gyun Chung, Keshab K. Parhi. Low error fixed-width CSD multiplier with efficient sign extension
994 -- 1001Joel H. Vuolevi, Timo Rahkonen. Analysis of third-order intermodulation distortion in common-emitter BJT and HBT amplifiers
1002 -- 1007Morteza Vadipour. Gradient error cancellation and quadratic error reduction in unary and binary D/A converters
1007 -- 1010Andrea Bonfanti, F. Amorosa, Carlo Samori, Andrea L. Lacaita. A DDS-based PLL for 2.4-GHz frequency synthesis
1011 -- 1015Ángel M. Bravo, Fernando Cruz-Roldán. Digital quadrature demodulator with four phases mixing for digital radio receivers
1016 -- 1023Gennaro Evangelista. Roundoff noise analysis in digital systems for arbitrary sampling rate conversion
1023 -- 1026Wei Xing Zheng 0001. Adaptive filter design subject to output envelope constraints and bounded input noise

Volume 50, Issue 11

773 -- 774Michael H. Perrott, Gu-Yeon Wei. Guest editorial
775 -- 783Youngdon Choi, Deog Kyoon Jeong, Wontae Kim. Jitter transfer analysis of tracked oversampling techniques for multigigabit clock and data recovery
784 -- 793Bram De Muer, Michiel S. J. Steyaert. On the analysis of /spl Delta//spl Sigma/ fractional-N frequency synthesizers for high-spectral purity
794 -- 803Tom A. D. Riley, Norman M. Filiol, Qinghong Du, Juha Kostamovaara. Techniques for in-band phase noise reduction in /spl Delta//spl Sigma/ synthesizers
804 -- 814Gabriele Manganaro, Sung U. Kwak, SeongHwan Cho, Anurag Pulincherry. A behavioral modeling approach to the design of a low jitter clock source
815 -- 828Robert Bogdan Staszewski, Dirk Leipold, Khurram Muhammad, Poras T. Balsara. Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process
829 -- 838Sudhakar Pamarti, Ian Galton. Phase-noise cancellation design tradeoffs in delta-sigma fractional-N PLLs
839 -- 849S. E. Meninger, Michael H. Perrott. A fractional- N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise
850 -- 859Marco Cassia, Peter Shah, Erik Bruun. Analytical model and behavioral simulation approach for a /spl Sigma//spl Delta/ fractional-N synthesizer employing a sample-hold element
860 -- 869Jaeha Kim, Mark A. Horowitz, Gu-Yeon Wei. Design of CMOS adaptive-bandwidth PLL/DLLs: a general approach
870 -- 878M. Mansuri, A. Hadiashar, Chih-Kong Ken Yang. Methodology for on-chip adaptive jitter minimization in phase-locked loops
879 -- 886Pavan Kumar Hanumolu, Bryan Casper, Randy Mooney, Gu-Yeon Wei, Un-Ku Moon. Analysis of PLL clock jitter in high-speed serial links
887 -- 892Robert Bogdan Staszewski, Dirk Leipold, Poras T. Balsara. Just-in-time gain estimation of an RF digitally-controlled oscillator for digital direct frequency modulation
892 -- 896Kuo-Hsing Cheng, Wei-Bin Yang, Cheng-ming Ying. A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop
896 -- 900G. Idei, H. Kunieda. A false-lock-free clock/data recovery PLL for NRZ data using adaptive phase frequency detector

Volume 50, Issue 10

673 -- 674J. Silva-Martinez. Guest editorial
675 -- 684Jingyu Huang, R. R. Spencer. The design of analog front ends for 1000BASE-T receivers
685 -- 694W. B. Kuhn, Dan Nobbe, D. Kelly, A. W. Orsborn. Dynamic range performance of on-chip RF bandpass filters
695 -- 704Roberto Gómez-García, José I. Alonso, Cesar Briso-Rodríguez. On the design of high-linear and low-noise two-branch channelized active bandpass filters
705 -- 713Bogdan Georgescu, Holly Pekau, James W. Haslett, John G. McRory. Tunable coupled inductor Q-enhancement for parallel resonant LC tanks
714 -- 727Yorgos Palaskas, Yannis P. Tsividis. Dynamic range optimization of weakly nonlinear, fully balanced, Gm-C filters with power dissipation constraints
728 -- 741Eric A. M. Klumperink, Bram Nauta. Systematic comparison of HF CMOS transconductors
742 -- 754Ahmed A. Emira, Edgar Sánchez-Sinencio. A pseudo differential complex filter for Bluetooth with frequency tuning
755 -- 761Taner Sumesaglam, Aydin I. Karsilayan. A digital approach for automatic tuning of continuous-time high-Q filters
762 -- 770A. N. Mohieldin, Edgar Sánchez-Sinencio, José Silva-Martínez. Nonlinear effects in pseudo differential OTAs with CMFB

Volume 50, Issue 1

1 -- 11Rola A. Baki, C. Beainy, Mourad N. El-Gamal. Distortion analysis of high-frequency log-domain filters using Volterra series
12 -- 30Ngai Wong, Tung-Sang Ng. DC stability analysis of high-order, lowpass /spl Sigma//spl Delta/ modulators with distinct unit circle NTF zeros
31 -- 37Omid Oliaei. State-space analysis of clock jitter in continuous-time oversampling data converters
38 -- 45Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang. Recursive architectures for realizing modified discrete cosine transform and its inverse