Journal: ACM Trans. Design Autom. Electr. Syst.

Volume 20, Issue 4

47 -- 0Hai-Bao Chen, Ying-Chi Li, Sheldon X.-D. Tan, Xin Huang, Hai Wang, Ngai Wong. H-Matrix-Based Finite-Element-Based Thermal Analysis for 3D ICs
48 -- 0Karel Heyse, Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt. TCONMAP: Technology Mapping for Parameterised FPGA Configurations
49 -- 0Steffen Peter, Tony Givargis. Component-Based Synthesis of Embedded Systems Using Satisfiability Modulo Theories
50 -- 0Ali Mirtar, Sujit Dey, Anand Raghunathan. An Application Adaptation Approach to Mitigate the Impact of Dynamic Thermal Management on Video Encoding
51 -- 0Da-Wei Chang, Hsin-Hung Chen, Wei-Jian Su. VSSD: Performance Isolation in a Solid-State Drive
52 -- 0Qing Duan, Abhishek Koneru, Jun Zeng, Krishnendu Chakrabarty, Gary Dispoto. Accurate Analysis and Prediction of Enterprise Service-Level Performance
53 -- 0Ingoo Heo, Minsu Kim, Yongje Lee, Changho Choi, JinYong Lee, Brent ByungHoon Kang, Yunheung Paek. Implementing an Application-Specific Instruction-Set Processor for System-Level Dynamic Program Analysis Engines
54 -- 0Lei Jiang, Bo Zhao, Jun Yang, Youtao Zhang. Constructing Large and Fast On-Chip Cache for Mobile Processors with Multilevel Cell STT-MRAM Technology
55 -- 0Mohammad Hossein Samavatian, Mohammad Arjomand, Ramin Bashizade, Hamid Sarbazi-Azad. Architecting the Last-Level Cache for GPUs using STT-RAM Technology
56 -- 0Leandro Soares Indrusiak, James Harbin, Osmar Marchi dos Santos. Fast Simulation of Networks-on-Chip with Priority-Preemptive Arbitration
57 -- 0Irith Pomeranz. FOLD: Extreme Static Test Compaction by Folding of Functional Test Sequences
58 -- 0Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik. Built-In Self-Test and Test Scheduling for Interposer-Based 2.5D IC
59 -- 0R. Iris Bahar, Alex K. Jones, Yuan Xie. Introduction to the Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems
60 -- 0Bradley T. Kiddie, William H. Robinson, Daniel B. Limbrick. Single-Event Multiple-Transient Characterization and Mitigation via Alternative Standard Cell Placement Methods
61 -- 0Leila Delshadtehrani, Hamed Farbeh, Seyed Ghassem Miremadi. In-Scratchpad Memory Replication: Protecting Scratchpad Memories in Multicore Embedded Systems against Soft Errors
62 -- 0Nikolaos Papandreou, Thomas P. Parnell, Haralampos Pozidis, Thomas Mittelholzer, Evangelos Eleftheriou, Charles Camp, Thomas Griffin, Gary A. Tressler, Andrew Walls. Enhancing the Reliability of MLC NAND Flash Memory Systems by Read Channel Optimization
63 -- 0Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie 0001. Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design
64 -- 0Renyuan Zhang, Mineo Kaneko. Robust and Low-Power Digitally Programmable Delay Element Designs Employing Neuron-MOS Mechanism
65 -- 0HyungJun Kim, Siva Bhanu Krishna Boga, Arseniy Vitkovskiy, Stavros Hadjitheophanous, Paul V. Gratz, Vassos Soteriou, Maria K. Michael. Use It or Lose It: Proactive, Deterministic Longevity in Future Chip Multiprocessors
66 -- 0Andrew B. Kahng, Seokhyeong Kang, Jiajia Li, José Pineda de Gyvez. An Improved Methodology for Resilient Design Implementation

Volume 20, Issue 3

34 -- 0Meeta Srivastav, Mohammed Ehteshamuddin, Kyle Stegner, Leyla Nazhandali. Design of Ultra-Low Power Scalable-Throughput Many-Core DSP Applications
35 -- 0Fahimeh Jafari, Zhonghai Lu, Axel Jantsch. Least Upper Delay Bound for VBR Flows in Networks-on-Chip with Virtual Channels
36 -- 0Nicola Bombieri, Franco Fummi, Sara Vinco. A Methodology to Recover RTL IP Functionality for Automatic Generation of SW Applications
37 -- 0Stefan Holst, Michael E. Imhof, Hans-Joachim Wunderlich. High-Throughput Logic Timing Simulation on GPGPUs
38 -- 0Tong Xu, Peng Li, Savithri Sundareswaran. Decoupling Capacitance Design Strategies for Power Delivery Networks with Power Gating
39 -- 0Farshad Firouzi, Fangming Ye, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori. Aging- and Variation-Aware Delay Monitoring Using Representative Critical Path Selection
40 -- 0HeeJong Park, Avinash Malik, Zoran A. Salcic. Scheduling Globally Asynchronous Locally Synchronous Programs for Guaranteed Response Times
41 -- 0Qiuping Yi, Zijiang Yang, Jian Liu, Chen Zhao, Chao Wang. Explaining Software Failures by Cascade Fault Localization
42 -- 0Jong Chul Lee, Roman L. Lysecky. System-Level Observation Framework for Non-Intrusive Runtime Monitoring of Embedded Systems
43 -- 0Qi Zhang, Xuandong Li, Linzhang Wang, Tian Zhang, Yi Wang 0003, Zili Shao. Lazy-RTGC: A Real-Time Lazy Garbage Collection Mechanism with Jointly Optimizing Average and Worst Performance for NAND Flash Memory Storage Systems
44 -- 0Namita Sharma, Preeti Ranjan Panda, Francky Catthoor, Praveen Raghavan, Tom Vander Aa. Array Interleaving - An Energy-Efficient Data Layout Transformation
45 -- 0Sudip Roy 0001, Partha Pratim Chakrabarti, Srijan Kumar, Krishnendu Chakrabarty, Bhargab B. Bhattacharya. Layout-Aware Mixture Preparation of Biochemical Fluids on Application-Specific Digital Microfluidic Biochips
46 -- 0Chandra K. H. Suresh, Sule Ozev, Ozgur Sinanoglu. Adaptive Generation of Unique IDs for Digital Chips through Analog Excitation

Volume 20, Issue 2

17 -- 0Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis Jen-Hsin Huang, Chin-Chi Teng, Chung-Kuan Cheng. ePlace: Electrostatics-Based Placement Using Fast Fourier Transform and Nesterov's Method
18 -- 0Qi Guo, Tianshi Chen, Zhi-Hua Zhou, Olivier Temam, Ling Li, Depei Qian, Yunji Chen. Robust Design Space Modeling
19 -- 0Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen. Yield Improvement for 3D Wafer-to-Wafer Stacked ICs Using Wafer Matching
20 -- 0Naiwen Chang, Eddie Cheng, Sunyuan Hsieh. Conditional Diagnosability of Cayley Graphs Generated by Transposition Trees under the PMC Model
21 -- 0Qing Duan, Jun Zeng, Krishnendu Chakrabarty, Gary Dispoto. Data-Driven Optimization of Order Admission Policies in a Digital Print Factory
22 -- 0Cheng-Yen Lin, Chung-Wen Huang, Chi-Bang Kuan, Shi-Yu Huang, Jenq Kuen Lee. The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore Systems
23 -- 0Marjan Asadinia, Mohammad Arjomand, Hamid Sarbazi-Azad. Prolonging Lifetime of PCM-Based Main Memories through On-Demand Page Pairing
24 -- 0Xing Huang, Genggeng Liu, Wenzhong Guo, Yuzhen Niu, Guolong Chen. Obstacle-Avoiding Algorithm in X-Architecture Based on Discrete Particle Swarm Optimization for VLSI Design
25 -- 0Hung-Sheng Chang, Yuan-Hao Chang, Pi-Cheng Hsiu, Tei-Wei Kuo, Hsiang-Pang Li. Marching-Based Wear-Leveling for PCM-Based Storage Systems
26 -- 0Gang Chen, Kai Huang 0001, Christian Buckl, Alois Knoll. Applying Pay-Burst-Only-Once Principle for Periodic Power Management in Hard Real-Time Pipelined Multiprocessor Systems
27 -- 0Franck Yonga, Michael Mefenza, Christophe Bobda. ASP-Based Encoding Model of Architecture Synthesis for Smart Cameras in Distributed Networks
28 -- 0Lok-Won Kim, Dong-U Lee, John D. Villasenor. Automated Iterative Pipelining for ASIC Design
29 -- 0Irith Pomeranz. A Generalized Definition of Unnecessary Test Vectors in Functional Test Sequences
30 -- 0Rafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich. Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation
31 -- 0Kamel Beznia, Ahcène Bounceur, Reinhardt Euler, Salvador Mir. A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters
32 -- 0Adwait Gupte, Sudhanshu Vyas, Phillip H. Jones. A Fault-Aware Toolchain Approach for FPGA Fault Tolerance
33 -- 0Jiliang Zhang, Yaping Lin, Gang Qu. Reconfigurable Binding against FPGA Replay Attacks

Volume 20, Issue 1

1 -- 0Naehyuck Chang, David Z. Pan, Yuan Xie 0001. Editorial: ACM Transactions on Design Automation of Electronics Systems and Beyond
2 -- 0Wei Hu, Dejun Mu, Jason Oberg, Baolei Mao, Mohit Tiwari, Timothy Sherwood, Ryan Kastner. Gate-Level Information Flow Tracking for Security Lattices
3 -- 0Chun-Kai Wang, Yeh-Chi Chang, Hung-Ming Chen, Ching-Yu Chin. Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation
4 -- 0Lingyi Liu, Shobha Vasudevan. Scaling Input Stimulus Generation through Hybrid Static and Dynamic Analysis of RTL
5 -- 0Sharad Sinha, Thambipillai Srikanthan. Dataflow Graph Partitioning for Area-Efficient High-Level Synthesis with Systems Perspective
6 -- 0Graeme Gange, Harald Søndergaard, Peter J. Stuckey. Synthesizing Optimal Switching Lattices
7 -- 0An-Che Cheng, Chia-Chih Jack Yen, Celina G. Val, Sam Bayless, Alan J. Hu, Iris Hui-Ru Jiang, Jing-Yang Jou. Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog
8 -- 0Xueliang Li, Guihai Yan, Yinhe Han, Xiaowei Li 0001. SmartCap: Using Machine Learning for Power Adaptation of Smartphone's Application Processor
9 -- 0Wen-Li Shih, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee. Compiler Optimization for Reducing Leakage Power in Multithread BSP Programs
10 -- 0Bojan Maric, Jaume Abella, Francisco J. Cazorla, Mateo Valero. Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation
11 -- 0Seungcheol Baek, Hyung Gyu Lee, Chrysostomos Nicopoulos, Jongman Kim. Designing Hybrid DRAM/PCM Main Memory Systems Utilizing Dual-Phase Compression
12 -- 0Hsien-Kai Kuo, Bo-Cheng Charles Lai, Jing-Yang Jou. Reducing Contention in Shared Last-Level Cache for Throughput Processors
13 -- 0Roopak Sinha, Alain Girault, Gregor Goessler, Partha S. Roop. A Formal Approach to Incremental Converter Synthesis for System-on-Chip Design
14 -- 0Levent Aksoy, Paulo F. Flores, José C. Monteiro. Multiplierless Design of Folded DSP Blocks
15 -- 0Mohamed Asan Basiri M., Sk. Noor Mahammad. An Efficient Hardware-Based Higher Radix Floating Point MAC Design
16 -- 0Cristiana Bolchini, Chiara Sandionigi. Design of Hardened Embedded Systems on Multi-FPGA Platforms