External Links

    Journal: TRETS

    Volume 13, Issue 4

    0 -- 0Anuj Vaishnav, Khoa Dang Pham, Joseph Powell, Dirk Koch. FOS: A Modular FPGA Operating System for Dynamic Workloads
    0 -- 0Aggelos D. Ioannou, Konstantinos Georgopoulos, Pavlos Malakonakis, Dionisios N. Pnevmatikatos, Vassilis D. Papaefstathiou, Ioannis Papaefstathiou, Iakovos Mavroidis. UNILOGIC: A Novel Architecture for Highly Parallel Reconfigurable Systems
    0 -- 0Jialiang Zhang, Yue Zha, Nicholas Beckwith, Bangya Liu, Jing Li 0073. MEG: A RISCV-based System Emulation Infrastructure for Near-data Processing Using FPGAs and High-bandwidth Memory
    0 -- 0André DeHon. Introduction to Special Section on FCCM 2019
    0 -- 0Yun Zhou, Dries Vercruyce, Dirk Stroobandt. Accelerating FPGA Routing Through Algorithmic Enhancements and Connection-aware Parallelization

    Volume 13, Issue 3

    0 -- 0Zhiyuan Shao, Chenhao Liu, Ruoshi Li, Xiaofei Liao, Hai Jin 0001. Processing Grid-format Real-world Graphs on DRAM-based FPGA Accelerators with Application-specific Caching Mechanisms
    0 -- 0Tuan Minh La, Kaspar Matas, Nikola Grunchevski, Khoa Dang Pham, Dirk Koch. FPGADefender: Malicious Self-oscillator Scanning for Xilinx UltraScale + FPGAs
    0 -- 0Sebastian Sabogal, Alan D. George, Christopher M. Wilson. Reconfigurable Framework for Environmentally Adaptive Resilience in Hybrid Space Systems
    0 -- 0Jiandong Mu, Wei Zhang 0012, Hao Liang, Sharad Sinha. Optimizing OpenCL-Based CNN Design on FPGA with Comprehensive Design Space Exploration and Collaborative Performance Modeling
    0 -- 0Qi Tang 0002, Zhe Wang, Biao Guo, Li-Hua Zhu, Ji-Bo Wei. Partitioning and Scheduling with Module Merging on Dynamic Partial Reconfigurable FPGAs
    0 -- 0Mohamed Eldafrawy, Andrew Boutros, Sadegh Yazdanshenas, Vaughn Betz. FPGA Logic Block Architectures for Efficient Deep Learning Inference

    Volume 13, Issue 2

    0 -- 0Maciej Besta, Marc Fischer, Tal Ben-Nun, Dimitri Stanojevic, Johannes de Fine Licht, Torsten Hoefler. Substream-Centric Maximum Matchings on FPGA
    0 -- 0Kevin E. Murray, Oleg Petelin, Sheng Zhong, Jia-Min Wang, Mohamed Eldafrawy, Jean-Philippe Legault, Eugene Sha, Aaron Graham, Jean Wu, Matthew J. P. Walker, Hanqing Zeng, Panagiotis Patros, Jason Luu, Kenneth B. Kent, Vaughn Betz. VTR 8: High-performance CAD and Customizable FPGA Architecture Modelling
    0 -- 0Yann Delomier, Bertrand Le Gal, Jérémie Crenne, Christophe Jégo. Model-based Design of Hardware SC Polar Decoders for FPGAs
    0 -- 0Nicholas J. Fraser, Philip H. W. Leong. Kernel Normalised Least Mean Squares with Delayed Model Adaptation
    0 -- 0Tushar Garg, Saud Wasly, Rodolfo Pellizzoni, Nachiket Kapre. HopliteBuf: Network Calculus-Based Design of FPGA NoCs with Provably Stall-Free FIFOs

    Volume 13, Issue 1

    0 -- 0Nikolaos Alachiotis, Charalampos Vatsolakis, Grigorios Chrysos 0001, Dionisios N. Pnevmatikatos. RAiSD-X: A Fast and Accurate FPGA System for the Detection of Positive Selection in Thousands of Genomes
    0 -- 0Sameh Attia, Vaughn Betz. Feel Free to Interrupt: Safe Task Stopping to Enable FPGA Checkpointing and Context Switching
    0 -- 0Al-Shahna Jamal, Eli Cahill, Jeffrey Goeders, Steven J. E. Wilton. Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays
    0 -- 0Alexandra Kourfali, Dirk Stroobandt. In-Circuit Debugging with Dynamic Reconfiguration of FPGA Interconnects
    0 -- 0François Serre, Markus Püschel. DSL-Based Hardware Generation with Scala: Example Fast Fourier Transforms and Sorting Networks
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