Journal: VLSI Design

Volume 2000, Issue 4

0 -- 0Carl L. Gardner. Guest Editorial
311 -- 320Bogdan J. Falkowski, Chip-Hong Chang. k-Variable-Mixed-Polarity Reed-Muller Expansions
321 -- 329Antonio J. López-Martín, Alfonso Carlosena. Design of MOS-translinear Multiplier/Dividers in Analog VLSI
331 -- 338Chua-Chin Wang, Chenn-Jung Huang, I-Yen Chang. Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library
335 -- 354Angelo Marcello Anile, O. Muscato, Vittorio Romano. Moment Equations with Maximum Entropy Closure for Carrier Transport in Semiconductor Devices: Validation in Bulk Silicon
339 -- 351D. Torres Roman, J. Gonzalez, M. Guzman. A New Bus Assignment Algorithm for a Shared Bus Switch Fabric
353 -- 361Chua-Chin Wang, Chenn-Jung Huang, Po-Ming Lee. Design and Analysis of Digital Ratioed Compressors for Inner Product Processing
355 -- 389W. Batty, A. J. Panks, R. G. Johnson, Christopher M. Snowden. Electro-thermal Modelling of Monolithic and Hybrid Microwave and Millimeter Wave IC's
363 -- 379Andrew G. Dempster. Graphical Design Techniques for Fixed-point Multiplication
381 -- 396Chaeryung Park, Taewhan Kim, C. L. Liu 0001. An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization
391 -- 414. Advanced Numerical Methods and Software Approaches for Semiconductor Device Simulation
397 -- 403S. Masupe, Tughrul Arslan. Low Power VLSI Implementation of the DCT on Single Multiplier DSP Processors
405 -- 415D. Torres Roman, A. Larios, M. Guzman. A Chip for a Routing Table Based on a Novel Modified Trie Algorithm
415 -- 435Carl L. Gardner, Christian A. Ringhofer. The Chapman-Enskog Expansion and the Quantum Hydrodynamic Model for Semiconductor Devices
437 -- 452Warren J. Gross, Dragica Vasileska, David K. Ferry. 3D Simulations of Ultra-small MOSFETs with Real-space Treatment of the Electron - Electron and Electron-ion Interactions
453 -- 466Joseph W. Jerome. Analytical and Computational Advances for Hydrodynamic Models of Classical and Quantum Charge Transport
467 -- 483Susanna Reggiani, Marina Valdinoci, Luigi Colalongo, Massimo Rudan, Giorgio Baccarani. An Analytical, Temperature-dependent Model for Majority- and Minority-carrier Mobility in Silicon Devices
485 -- 529. Discretization of Anisotropic Convection-diffusion Equations, Convective M-matrices and their Iterative Solution

Volume 2000, Issue 3

0 -- 0Youssef Saab. Guest Editorial
0 -- 0Jack Jean, Sanjaya Kumar. Guest Editorial
175 -- 218Sao-Jie Chen, Chung-Kuan Cheng. Tutorial on VLSI Partitioning
219 -- 235Huiqun Liu, Kai Zhu, D. F. Wong. FPGA Partitioning with Complex Resource Constraints
237 -- 248R. P. Bazylevych, R. A. Melnyk, O. G. Rybak. Circuit Partitioning for FPGAs by the Optimal Circuit Reduction Method
249 -- 258Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov. Iterative Partitioning with Varying Node Weights
249 -- 263Zhen Luo, Margaret Martonosi, Pranav Ashar. An Edge-endpoint-based Configurable Hardware Architecture for VLSI Layout Design Rule Checking
259 -- 283Shawki Areibi, Anthony Vannelli. Tabu Search: A Meta Heuristic for Netlist Partitioning
265 -- 279Brian Schott, Stephen P. Crago, Robert Parker, Chen H. Chen, Lauretta C. Carter, Joseph Czarnaski, Matthew French, Ivan Hom, Tam Tho, Terri Valenti. Reconfigurable Architectures for System Level Applications of Adaptive Computing
281 -- 306Ted Bapty, Sandeep Neema, Jason Scott, Janos Sztipanovits, Sameh Asaad. Model-integrated Tools for the Design of Dynamically Reconfigurable Systems
285 -- 300George Karypis, Vipin Kumar. k-way Hypergraph Partitioning
301 -- 310Youssef Saab. A New 2-way Multi-level Partitioning Algorithm
307 -- 319Marco A. Figueiredo, Clay S. Gloster Jr., Mark A. Stephens, Corey A. Graves, Mouna Nakkar. Implementation of Multispectral Image Classification on a Remote Adaptive Computer
321 -- 333Chi-Feng Wu, Cheng-Wen Wu. Testing and Diagnosing Dynamic Reconfigurable FPGA

Volume 2000, Issue 2

75 -- 84L. M. Patnaik, Satrajit Gupta. Exact Output Response Computation of RC Interconnects Under General Polynomial Input Waveforms
85 -- 105Bogdan J. Falkowski, Radomir S. Stankovic. Spectral Interpretation and Applications of Decision Diagrams
107 -- 113Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen. A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop
115 -- 128Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici. A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic
129 -- 136Esther Rodríguez-Villegas, Maria J. Avedillo, José M. Quintana, Gloria Huertas, Adoración Rueda. νMOS-based Sorter for Arithmetic Applications
137 -- 147Yanjun Zhang, Si-Qing Zheng. An Efficient Parallel VLSI Sorting Architecture
149 -- 159Chien-In Henry Chen, Yingjie Zhou. Configurable 2-D Linear Feedback Shift Registers for VLSI Built-in Self-test Designs
161 -- 173Dong Wook Kim, Tae-Yong Choi. Delay Time Estimation Model for Large Digital CMOS Circuits

Volume 2000, Issue 1

0 -- 0Parag K. Lala. Guest Editorial
1 -- 21Alexej Dmitriev, V. V. Saposhnikov, Vl. V. Saposhnikov, Michael Gössel, V. Moshanin, Andrej A. Morosov. New Self-dual Circuits for Error Detection and Testing
23 -- 34Cecilia Metra, Michele Favalli, Bruno Riccò. Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-checking Circuits
35 -- 45Xrysovalantis Kavousianos, Dimitris Nikolos, G. Sidiropoulos. n Codes
47 -- 58Anzhela Yu. Matrosova, I. Levin, Sergey Ostanin. Self-checking Synchronous FSM Network Design with Low Overhead
59 -- 74Emmanuel Simeu. Optimal Detector Design for On-line Testing of Linear Analog Systems