Journal: VLSI Signal Processing

Volume 16, Issue 2-3

113 -- 116Eby G. Friedman. High Performance Clock Distribution Networks
117 -- 130Luca Benini, Patrick Vuillod, Alessandro Bogliolo, Giovanni De Micheli. Clock Skew Optimization for Peak Current Reduction
131 -- 147Hong-Yean Hsieh, Wentai Liu, Paul D. Franzon, Ralph K. Cavin III. Clocking Optimization and Distribution in Digital Systems with Scheduled Skews
149 -- 161José Luis Neves, Eby G. Friedman. Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations
163 -- 179Joe G. Xi, Wayne Wei-Ming Dai. Useful-Skew Clock Routing with Gate Sizing for Low Power Design
181 -- 189Shantanu Ganguly, Daksh Lehther, Satyamurthy Pullela. Clock Distribution Methodology for PowerPC:::TM::: Microprocessors
191 -- 198David J. Hathaway, Rafik R. Habra, Erich C. Schanzenbach, Sara J. Rothman. Circuit Placement, Chip Optimization, and Wire Routing for IBM IC Technology
199 -- 215Andrew B. Kahng, Chung-Wen Albert Tsao. Practical Bounded-Skew Clock Routing
217 -- 224Keith M. Carrig, Albert M. Chu, Frank D. Ferraiolo, John G. Petrovick, P. Andrew Scott, Richard J. Weiss. A Clock Methodology for High-Performance Microprocessors
225 -- 246Stuart K. Tewksbury, Lawrence A. Hornak. Optical Clock Distribution in Electronic Systems
247 -- 276Kris Gaj, Eby G. Friedman, Marc J. Feldman. Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits

Volume 16, Issue 1

5 -- 7Keshab K. Parhi, Takao Nishitani, Hironori Yamauchi. Guest Editors Introduction
9 -- 23Won Namgoong, Teresa H. Y. Meng. A Low-Power Encoder For Pyramid Vector Quantization of Subband Coefficients
25 -- 30Masahiro Iwadare, Hideto Takano, Yoshitaka Shibuya, Hideki Sakamoto, Takeshi Kuwajima, Osamu Kitabatake, Naoko Kobayashi. A Single-Chip MPEG/Audio Decoder LSI Based on a Compact Decoding Algorithm
31 -- 40Johannes Kneip, Mladen Berekovic, Jens Peter Wittenburg, Willm Hinrichs, Peter Pirsch. An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor
41 -- 55David W. Trainor, Roger F. Woods, John V. McCanny. Architectural Synthesis of Digital Signal Processing Algorithms Using IRIS
57 -- 72Kazuhito Ito, Keshab K. Parhi. A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis
73 -- 80Vojin Zivojnovic, Steven W. K. Tjiang, Heinrich Meyr. Compiled Simulation of Programmable DSP Architectures
81 -- 103Anissa Zergaïnoh, Pierre Duhamel, Jean Pierre Vidal. Efficient Implementation Methodology of Fast FIR Filtering Algorithms on DSP