| 5 | -- | 0 | Mohammad Ibrahim, Earl E. Swartzlander Jr.. Guest Editorial |
| 7 | -- | 18 | Marc Daumas, David W. Matula. Further Reducing the Redundancy of a Notation Over a Minimally Redundant Digit Set |
| 19 | -- | 29 | Jen-Chuan Chih, Sau-Gee Chen. Fast CORDIC Algorithm Based on a New Recoding Scheme for Rotation Angles and Variable Scale Factors |
| 31 | -- | 35 | Vincent Lefèvre, Jean-Michel Muller. On-the-Fly Range Reduction |
| 37 | -- | 53 | Mark G. Arnold, Thomas A. Bailey, John R. Cowles. Error Analysis of the Kmetz/Maenner Algorithm |
| 55 | -- | 74 | Javier D. Bruguera, Tomás Lang. Multilevel Reverse-Carry Addition: Single and Dual Adders |
| 75 | -- | 82 | Vasily G. Moshnyaga. Reducing Switching Activity of Subtraction via Variable Truncation of the Most-Significant Bits |
| 83 | -- | 103 | Dusan Suvakovic, C. Andre T. Salama. Energy Efficient Adiabatic Multiplier-Accumulator Design |
| 105 | -- | 115 | T. Sansaloni, Javier Valls, Keshab K. Parhi. Digit-Serial Complex-Number Multipliers on FPGAs |
| 117 | -- | 124 | Jen-Shiun Chiang, Min-Shiou Tsai. A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling |
| 125 | -- | 145 | Álvaro Vázquez, Elisardo Antelo. Implementation of the Exponential Function in a Floating-Point Unit |
| 147 | -- | 155 | Jiun-In Guo, Jui-Cheng Yen. An Efficient IDCT Processor Design for HDTV Applications |
| 157 | -- | 169 | Pol-Lin Tai, Chii-Tung Liu, Jia-Shung Wang. An Integrated Systolic Array Design for Video Compression |
| 171 | -- | 190 | Javier Ramírez, Antonio García, Uwe Meyer-Bäse, Fred J. Taylor, Antonio Lloris-Ruíz. Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic |
| 191 | -- | 197 | Xingjun Wu, Hongyi Chen, Yihe Sun, Weixin Gai. A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems |
| 199 | -- | 220 | Massimo Panella, Giuseppe Martinelli. An RNS Architecture for Quasi-Chaotic Oscillators |