Impact of Leakage Power Reduction Techniques on Parametric Yield - Low-Power Design of Digital Integrated Circuits under Process Parameter Variations

Sudip Roy 0001, Ajit Pal. Impact of Leakage Power Reduction Techniques on Parametric Yield - Low-Power Design of Digital Integrated Circuits under Process Parameter Variations. LAP Lambert Academic Publishing, 2013.

Abstract

Abstract is missing.