Abstract is missing.
- Micro-XRD investigation of fine-pitch Cu-TSV induced thermo-mechanical stress in high-density 3D-LSIMariappan Murugesan, Takafumi Fukushima, Ji Chel Bea, K. W. Lee, M. Koyanagi, Y. Imai, S. Kimura, Tetsu Tanaka. 1-4 [doi]
- Designing vertical bandwidth reconfigurable 3D NoCs for many core systemsQiaosha Zou, Jia Zhan, Fen Ge, Matt Poremba, Yuan Xie 0001. 1-7 [doi]
- Electroless metal deposition for IC and TSV applicationsJames F. Rohan, Declan Casey, Monika Zygowska, Michael Moore, Brian Shanahan. 1-3 [doi]
- Innovative SiC over Si photodiode based dual-band, 3D integrated detectorA. Kociubinski, M. Duk, Tomasz Bieniek, Grzegorz Janczyk, M. Borecki. 1-4 [doi]
- Leveraging 3D-IC for on-chip timing uncertainty measurementsRandy Widialaksono, Wenxu Zhao, W. Rhett Davis, Paul D. Franzon. 1-4 [doi]
- Substrate monitoring system for inspecting defects in TSV-based data busesYuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi. 1-5 [doi]
- Advanced processing for high efficiency inductors for 2.5D/3D Power Supply in PackageRicky Anthony, Santosh Kulkarni, Ningning Wang, Seán Cian O. Mathuna. 1-4 [doi]
- Thermal effects of heterogeneous interconnects on InP / GaN / Si diverse integrated circuitsT. Robert Harris, Paul D. Franzon, W. Rhett Davis, Lee Wang. 1-3 [doi]
- Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementationSonda Chtourou, Mohamed Abid, Vinod Pangracious, Emna Amouri, Zied Marrakchi, Habib Mehrez. 1-7 [doi]
- Thermal performance of 3D ICs: Analysis and alternativesCristiano Santos, Pascal Vivet, Jean-Philippe Colonna, Perceval Coudrain, Ricardo Augusto da Luz Reis. 1-7 [doi]
- Manufacturing and test assistance for 3D-Integrated heterogeneous systemsArmin Gruenewald, Michael Wahl, Rainer Brueck. 1-6 [doi]
- 2 direct hybrid bondingYann Beilliard, Stéphane Moreau, Léa Di Cioccio, Perceval Coudrain, G. Romano, A. Nowodzinski, F. Aussenac, P.-H. Jouneau, E. Rolland, Thomas Signamarcheix. 1-8 [doi]
- Simple and low cost technique for stacking known good dies to create compact 3D stacked parallel optics assembliesO. Raz, P. Duan, H. J. S. Dorren. 1-4 [doi]
- Small-diameter TSV reveal process using direct Si/Cu grinding and metal contamination removalNaoya Watanabe, Masahiro Aoyagi, Daisuke Katagawa, Tsubasa Bandoh, Takahiko Mitsui, Eiichi Yamamoto. 1-5 [doi]
- Thermal challenges for heterogeneous 3D ICs and opportunities for air gap thermal isolationYang Zhang, Thomas E. Sarvey, Muhannad S. Bakir. 1-5 [doi]
- A built-in supply current test circuit for electrical interconnect tests of 3D ICsMasaki Hashizume, Shoichi Umezu, Hiroyuki Yotsuyanagi, Shyue-Kung Lu. 1-6 [doi]
- Advanced 3D mixed-signal processor for infrared focal plane arrays: Fabrication and testDorota S. Temple, Dean Malta, Erik P. Vick, Matthew R. Lueck, Scott H. Goodwin, Mark S. Muzilla, Christopher M. Masterjohn, Mark R. Skokan. 1-7 [doi]
- Electrical model and characterization of Through Silicon Capacitors (TSC) in silicon interposerKhadim Dieng, Philippe Artillan, Cédric Bermond, Olivier Guiller, Thierry Lacrevaz, Sylvain Joblot, Gregory Houzet, Alexis Farcy, Yann Lamy, Bernard Fléchet. 1-8 [doi]
- Effects of electro-less Ni layer as barrier/seed layers for high reliable and low cost Cu TSVK. W. Lee, C. Nagai, A. Nakamura, Ji Chel Bea, Mariappan Murugesan, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi. 1-4 [doi]
- Characterization of particle beds in percolating thermal underfills based on centrifugationSeverin Zimmermann, Thomas Brunschwiler, Brian R. Burg, Jonas Zuercher, Guo-Hong, Dimos Poulikakos, Mario Baum, Christian Hofmann. 1-7 [doi]
- Thermal implications of mobile 3D-ICsMehdi Saedi, Kambiz Samadi, Arpit Mittal, Rajat Mittal. 1-7 [doi]
- Modeling of substrate contacts in TSV-based 3D ICsMasayuki Watanabe, Masa-Aki Fukase, Masashi Imai, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Atsushi Kurokawa. 1-4 [doi]
- Magnetically-coupled current probing structure consisting of TSVs and RDLs in 2.5D and 3D ICsJonghoon J. Kim, Bumhee Bae, Sukjin Kim, Sunkyu Kong, Heegon Kim, Daniel H. Jung, Joungho Kim. 1-6 [doi]
- Cooling from the bottom side (laminate (substrate) side) of a three-dimensional (3D) chip stackKeiji Matsumoto, Hiroyuki Mori, Yasumitsu Orii. 1-6 [doi]
- Analysis of thermal stress distribution for TSV with novel structureWei Feng, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi. 1-4 [doi]
- Analysis and optimization of a power distribution network in 2.5D IC with glass interposerYoungWoo Kim, Jonghyun Cho, Kiyeong Kim, Heegon Kim, Joungho Kim, Srikrishna Sitaraman, Venky Sundaram, Rao R. Tummala. 1-4 [doi]
- Au-NiW Mechanically Flexible Interconnects (MFIs) and TSV integration for 3D interconnectsChaoqi Zhang, Paragkumar Thadesar, Muneeb Zia, Thomas E. Sarvey, Muhannad S. Bakir. 1-4 [doi]
- Impact of Thermomechanical Stresses on Ultra-thin Si Stacked StructureYoriko Mizushima, Young-Suk Kim, Tomoji Nakamura, Shoichi Kodama, Nobuhide Maeda, Koji Fujimoto, Takayuki Ohba. 1-5 [doi]
- Conventional magnetron sputtering of metal seed layers on high aspect ratio vias with tiltingYoung Sik Song, Yunho Han, Tai Hong Yim. 1-4 [doi]
- Cu seeding using electroless deposition on Ru liner for high aspect ratio through-Si viasFumihiro Inoue, Harold Philipsen, Marleen H. van der Veen, Kevin Vandersmissen, Stefaan Van Huylenbroeck, Herbert Struyf, Tetsu Tanaka. 1-4 [doi]
- Metal coated polymer spheres for compliant fine pitch ball grid arraysDaniel Nilsen Wright, Maaike M. Visser Taklo, Astrid-Sofie B. Vardøy, Helge Kristiansen. 1-7 [doi]
- On-chip checkpointing with 3D-stacked memoriesMasayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi. 1-6 [doi]
- Design rule check and layout versus schematic for 3D integration and advanced packagingRobert Fischbach, Andy Heinig, Peter Schneider. 1-7 [doi]
- An impact of circuit scale on the performance of 3-D stacked arithmetic unitsJubee Tada, Ryusuke Egawa, Hiroaki Kobayashi. 1-5 [doi]
- Comparative study of 3D stacked IC and 3D interposer integration: Processing and assembly challengesJoeri De Vos, Vladimir Cherman, Mikael Detalle, Teng Wang, Abdellah Salahouelhadj, Robert Daily, Geert Van der Plas, Eric Beyne. 1-7 [doi]
- 3D-enabled customizable embedded computer (3DECC)Paul D. Franzon, Eric Rotenberg, James Tuck, Huiyang Zhou, W. Rhett Davis, Hongwen Dai, Joonmoo Huh, Sunkgwan Ku, Steve Lipa, Chao Li, Jong Beom Park, Joshua Schabel. 1-3 [doi]
- A cost benefit analysis: The impact of defect clustering on the necessity of pre-bond testsQiaosha Zou, Matt Poremba, Yuan Xie 0001. 1-7 [doi]
- Tiny VCSEL chip self-assembly for advanced chip-to-wafer 3D and hetero integrationTakafumi Fukushima, Yuka Ito, Mariappan Murugesan, Jicheol Bea, Kang-Wook Lee, Koji Choki, Tetsu Tanaka, Mitsumasa Koyanagi. 1-4 [doi]
- Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integrationBui Thanh Tung, Xiaojin Cheng, Naoya Watanabe, Fumiki Kato, Katsuya Kikuchi, Masahiro Aoyagi. 1-4 [doi]
- Novel methodology for 3D MEMS-IC design and co-simulation on MEMS microphone smart system exampleTomasz Bieniek, Grzegorz Janczyk, Magdalena Ekwinska, T. Budzynski, Piotr Gluszko, Piotr Grabiec, A. Kociubinski. 1-5 [doi]
- Fault localisation of defects using Electro Optical Terahertz Pulse Reflectometry and 3D EM modelling with Virtual Known Good DeviceEmma Kowalczuk, Arnab Bhattacharya, Ka Chung Lee, Jesse Alton, Martin Igarashi, Stephane Barbeau. 1-4 [doi]
- Fault detection and isolation of multiple defects in through silicon via (TSV) channelDaniel H. Jung, Heegon Kim, Jonghoon J. Kim, Sukjin Kim, Joungho Kim, Hyun-Cheol Bae, Kwang-Seong Choi. 1-5 [doi]
- Using TSVs for thermal mitigation in 3D circuits: Wish and truthCristiano Santos, Papa Momar Souare, François de Crecy, Perceval Coudrain, Jean-Philippe Colonna, Pascal Vivet, Andras Borbely, Ricardo Reis, M. Haykel Ben Jamaa, Vincent Fiori, Alexis Farcy. 1-8 [doi]
- Bumpless interconnects formed with nanowire ACF for 3D applicationsJing Tao, Alan Mathewson, Kafil M. Razeeb. 1-6 [doi]
- Ultrawideband ultralow PDN impedance of decoupling capacitor embedded interposers using narrow gap chip parts mounting technology for 3-D integrated LSI systemKatsuya Kikuchi, Masahiro Aoyagi, Masaaki Ujiie, Shinya Takayama. 1-6 [doi]
- Analysis of 3D interconnect performance: Effect of the Si substrate resistivityX. Sun, Geert Van der Plas, Mikael Detalle, Eric Beyne. 1-4 [doi]