Feasibility of Parasitic Drain Inductance Design for Minimizing Switching Loss in Bridge Circuits Using GaN-FETs

Koki Abe, Masataka Ishihara, Yusuke Hatakenaka, Kazuhiro Umetani, Eiji Hiraki. Feasibility of Parasitic Drain Inductance Design for Minimizing Switching Loss in Bridge Circuits Using GaN-FETs. In 30th IEEE International Symposium on Industrial Electronics, ISIE 2021, Kyoto, Japan, June 20-23, 2021. pages 1-5, IEEE, 2021. [doi]

Abstract

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