GARNET: A detailed on-chip network model inside a full-system simulator

Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Niraj K. Jha. GARNET: A detailed on-chip network model inside a full-system simulator. In IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2009, April 26-28, 2009, Boston, Massachusetts, USA, Proceedings. pages 33-42, IEEE, 2009. [doi]

Abstract

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