A 5Gbps 0.13μm CMOS pilot-based clock and data recovery scheme for high-speed links

Mahmoud Reza Ahmadi, Amir Amirkhany, Ramesh Harjani. A 5Gbps 0.13μm CMOS pilot-based clock and data recovery scheme for high-speed links. In IEEE Custom Integrated Circuits Conference, CICC 2009, San Jose, California, USA, 13-16 September, 2009, Proceedings. pages 125-128, IEEE, 2009. [doi]

Abstract

Abstract is missing.