Wafer-level process variation-driven probe-test flow selection for test cost reduction in analog/RF ICs

Ali Ahmadi, Amit Nahar, Bob Orr, Michael Pas, Yiorgos Makris. Wafer-level process variation-driven probe-test flow selection for test cost reduction in analog/RF ICs. In 34th IEEE VLSI Test Symposium, VTS 2016, Las Vegas, NV, USA, April 25-27, 2016. pages 1-6, IEEE Computer Society, 2016. [doi]

Abstract

Abstract is missing.