A 8.7mW 5-Gb/s clock and data recovery circuit with 0.18-µm CMOS

Taek-Joon An, Kyung-Sub Son, Young-Jin Kim, In-Seok Kong, Jin-Ku Kang. A 8.7mW 5-Gb/s clock and data recovery circuit with 0.18-µm CMOS. In IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014. pages 2329-2332, IEEE, 2014. [doi]

Abstract

Abstract is missing.