A -245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS - researchr publication related

researchr

You are not signed in
Sign in
Sign up

Jens Anders, Sebastian Bader 0003, Markus Dietl, Puneet Sareen, G. Rombach, S. Tambouris, Maurits Ortmanns. A -245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017. pages 325-328, IEEE, 2017. [doi]

The following publications are possibly variants of this publication:

A BW-tracking semi-digital PLL with near-optimal VCO phase noise shaping in low-cost 0.4 µm CMOS achieving 700 fs rms phase jitterS. Fahmy, Markus Dietl, Puneet Sareen, Maurits Ortmanns, Jens Anders. norchip 2015: 1-4 [doi]

RMS Jitter, -260.2-dB FOM, and -70.96-dBc Reference SpurYunbo Huang, Yong Chen 0005, Bo Zhao 0003, Pui-In Mak, Rui Paulo Martins. tcasI, 70(4):1463-1475, April 2023. [doi]

runs on WebDSL