FPGA Implementation of a TVWS Up- and Downconverter Using Non-Power-of-Two FFT Modulated Filter Banks

Vianney Anis, Jincheng Guo, Stephan D. Weiss, Louise H. Crockett. FPGA Implementation of a TVWS Up- and Downconverter Using Non-Power-of-Two FFT Modulated Filter Banks. In 27th European Signal Processing Conference, EUSIPCO 2019, A Coruña, Spain, September 2-6, 2019. pages 1-5, IEEE, 2019. [doi]

@inproceedings{AnisGWC19,
  title = {FPGA Implementation of a TVWS Up- and Downconverter Using Non-Power-of-Two FFT Modulated Filter Banks},
  author = {Vianney Anis and Jincheng Guo and Stephan D. Weiss and Louise H. Crockett},
  year = {2019},
  doi = {10.23919/EUSIPCO.2019.8902588},
  url = {https://doi.org/10.23919/EUSIPCO.2019.8902588},
  researchr = {https://researchr.org/publication/AnisGWC19},
  cites = {0},
  citedby = {0},
  pages = {1-5},
  booktitle = {27th European Signal Processing Conference, EUSIPCO 2019, A Coruña, Spain, September 2-6, 2019},
  publisher = {IEEE},
  isbn = {978-9-0827-9703-9},
}