Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine. 4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR. In 18th IEEE/IFIP VLSI-SoC 2010, IEEE/IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Madrid, Spain, 27-29 September 2010. pages 364-368, IEEE, 2010. [doi]
Abstract is missing.