A 14-bit 100MS/s pipelined A/D converter with 2b interstage redundancy

Kun Ao, Yajuan He, Liang Li, Yuxin Wang, Qiang Li. A 14-bit 100MS/s pipelined A/D converter with 2b interstage redundancy. In 2014 International Symposium on Integrated Circuits (ISIC), Singapore, December 10-12, 2014. pages 83-86, IEEE, 2014. [doi]

Abstract

Abstract is missing.