A RISC Processor with Redundant LNS Instructions

Mark G. Arnold. A RISC Processor with Redundant LNS Instructions. In Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia. pages 475-482, IEEE Computer Society, 2006. [doi]

Abstract

Abstract is missing.