Seung-Jun Bae, Kwang-Il Park, Jeong-Don Ihm, Ho-Young Song, Woo Jin Lee, Hyun-Jin Kim, Kyoung-Ho Kim, Yoon-Sik Park, Min-Sang Park, Hong-Kyong Lee, Sam-Young Bang, Gil-Shin Moon, Seokwon Hwang, Young-Chul Cho, Sang-Jun Hwang, Dae-Hyun Kim, Ji-Hoon Lim, Jae-Sung Kim, Sunghoon Kim, Seong-Jin Jang, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim, Soo-In Cho. An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion. J. Solid-State Circuits, 43(1):121-131, 2008. [doi]
@article{BaePISLKKPPLBMH08,
title = {An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion},
author = {Seung-Jun Bae and Kwang-Il Park and Jeong-Don Ihm and Ho-Young Song and Woo Jin Lee and Hyun-Jin Kim and Kyoung-Ho Kim and Yoon-Sik Park and Min-Sang Park and Hong-Kyong Lee and Sam-Young Bang and Gil-Shin Moon and Seokwon Hwang and Young-Chul Cho and Sang-Jun Hwang and Dae-Hyun Kim and Ji-Hoon Lim and Jae-Sung Kim and Sunghoon Kim and Seong-Jin Jang and Joo-Sun Choi and Young-Hyun Jun and Kinam Kim and Soo-In Cho},
year = {2008},
doi = {10.1109/JSSC.2007.908002},
url = {https://doi.org/10.1109/JSSC.2007.908002},
researchr = {https://researchr.org/publication/BaePISLKKPPLBMH08},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {43},
number = {1},
pages = {121-131},
}