Raminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki. Instruction buffering to reduce power in processors for signal processing. IEEE Trans. VLSI Syst., 5(4):417-424, 1997. [doi]
Abstract is missing.