Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies - researchr publication related

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T. Huynh Bao, Dmitry Yakimets, Julien Ryckaert, Ivan Ciofi, R. Baert, A. Veloso, J. Bommels, Nadine Collaert, Philippe Roussel, S. Demuynck, Praveen Raghavan, Abdelkarim Mercha, Zsolt Tokei, Diederik Verkest, Aaron Thean, Piet Wambacq. Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. In 44th European Solid State Device Research Conference, ESSDERC 2014, Venice Lido, Italy, September 22-26, 2014. pages 102-105, IEEE, 2014. [doi]

The following publications are possibly variants of this publication:

Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAMTrong Huynh Bao, Sushil Sakhare, Julien Ryckaert, Dmitry Yakimets, Abdelkarim Mercha, Diederik Verkest, Aaron Voon-Yew Thean, Piet Wambacq. icicdt 2015: 1-4 [doi]

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