Thomas S. Barnett, Adit D. Singh, Victor P. Nelson. Yield-Reliability Modeling for Fault Tolerant Integrated Circuits. In 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings. pages 29-38, IEEE Computer Society, 2001. [doi]
Abstract is missing.