Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator - researchr publication

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Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess. Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator. IEEE Trans. on CAD of Integrated Circuits and Systems, 15(11):1424-1434, 1996. [doi]

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