Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit - researchr publication authors

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Debashis Bhattacharya, S. Freeman, W. Lin. Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit. In 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India. pages 289-296, IEEE Computer Society, 1997. [doi]

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