Debashis Bhattacharya, S. Freeman, W. Lin. Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit. In 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India. pages 289-296, IEEE Computer Society, 1997. [doi]
@inproceedings{BhattacharyaFL97, title = {Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit}, author = {Debashis Bhattacharya and S. Freeman and W. Lin}, year = {1997}, doi = {10.1109/ICVD.1997.568092}, url = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568092}, tags = {optimization, testing}, researchr = {https://researchr.org/publication/BhattacharyaFL97}, cites = {0}, citedby = {0}, pages = {289-296}, booktitle = {10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India}, publisher = {IEEE Computer Society}, }