A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores - researchr publication

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Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch. A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. In 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan. pages 253-258, IEEE Computer Society, 2001. [doi]

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