The following publications are possibly variants of this publication:
- Design of Routing-Constrained Low Power Scan ChainsYannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. date 2004: 62-67 [doi]
- Power-Driven Routing-Constrained Scan Chain DesignYannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch. et, 20(6):647-660, 2004. [doi]
- Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan RoutingPatrick Girard, Yannick Bonhomme. jolpe, 1(1):85-95, 2005. [doi]
- Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing ConstraintYannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch. itc 2003: 488-493 [doi]
- Circuit Partitioning for Low Power BIST Design with Minimized Peak Power ConsumptionPatrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch. ats 1999: 89-94 [doi]