Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis

Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer. Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis. In Robert Werner, editor, EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28 - March 3, 1994, Paris, France. pages 332-337, IEEE Computer Society, 1994.

Abstract

Abstract is missing.