Thomas Buerner. Implementation of a Successive Erasure BCH(16, 7, 6) Decoder and Performance Simulation by Rapid Prototyping. In Manfred Glesner, Peter Zipf, Michel Renovell, editors, Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings. Volume 2438 of Lecture Notes in Computer Science, pages 462-471, Springer, 2002. [doi]
Abstract is missing.