Adding instruction cache effect to schedulability analysis of preemptive real-time systems

José V. Busquets-Mataix, Juan José Serrano, Rafael Ors, Pedro J. Gil, Andy J. Wellings. Adding instruction cache effect to schedulability analysis of preemptive real-time systems. In 2nd IEEE Real-Time Technology and Applications Symposium (RTAS 96), June 10-12, 1996, Boston, MA, USA. pages 204, IEEE Computer Society, 1996. [doi]

Authors

José V. Busquets-Mataix

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Juan José Serrano

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Rafael Ors

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Pedro J. Gil

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Andy J. Wellings

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