Hybrid instruction cache partitioning for preemptive real-time systems

José V. Busquets-Mataix, Juan José Serrano, Andy J. Wellings. Hybrid instruction cache partitioning for preemptive real-time systems. In Proceedings of the Ninth Euromicro Workshop on Real-Time Systems, RTS 1997, 11-13 June, 1997, Toledo, Spain. pages 56-63, IEEE, 1997. [doi]

@inproceedings{Busquets-MataixSW97,
  title = {Hybrid instruction cache partitioning for preemptive real-time systems},
  author = {José V. Busquets-Mataix and Juan José Serrano and Andy J. Wellings},
  year = {1997},
  doi = {10.1109/EMWRTS.1997.613764},
  url = {http://doi.ieeecomputersociety.org/10.1109/EMWRTS.1997.613764},
  researchr = {https://researchr.org/publication/Busquets-MataixSW97},
  cites = {0},
  citedby = {0},
  pages = {56-63},
  booktitle = {Proceedings of the Ninth Euromicro Workshop on Real-Time Systems, RTS 1997, 11-13 June, 1997, Toledo, Spain},
  publisher = {IEEE},
  isbn = {0-8186-8036-9},
}