SystemVerilog Assertions: Past, Present, and Future SVA Standardization Experience

Doron Bustan, Dmitry Korchemny, Erik Seligman, Jin Yang. SystemVerilog Assertions: Past, Present, and Future SVA Standardization Experience. IEEE Design & Test of Computers, 29(2):23-31, 2012. [doi]

@article{BustanKSY12,
  title = {SystemVerilog Assertions: Past, Present, and Future SVA Standardization Experience},
  author = {Doron Bustan and Dmitry Korchemny and Erik Seligman and Jin Yang},
  year = {2012},
  doi = {10.1109/MDT.2012.2183336},
  url = {http://dx.doi.org/10.1109/MDT.2012.2183336},
  researchr = {https://researchr.org/publication/BustanKSY12},
  cites = {0},
  citedby = {0},
  journal = {IEEE Design & Test of Computers},
  volume = {29},
  number = {2},
  pages = {23-31},
}