A 256kb Sub-threshold SRAM in 65nm CMOS

Benton H. Calhoun, Anantha Chandrakasan. A 256kb Sub-threshold SRAM in 65nm CMOS. In 2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006. pages 2592-2601, IEEE, 2006. [doi]

Abstract

Abstract is missing.