Fast instruction cache modeling for approximate timed HW/SW co-simulation

Juan Castillo, Hector Posadas, Eugenio Villar, Marcos Martínez. Fast instruction cache modeling for approximate timed HW/SW co-simulation. In R. Iris Bahar, Fabrizio Lombardi, David Atienza, Erik Brunvand, editors, Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010. pages 191-196, ACM, 2010. [doi]

@inproceedings{CastilloPVM10,
  title = {Fast instruction cache modeling for approximate timed HW/SW co-simulation},
  author = {Juan Castillo and Hector Posadas and Eugenio Villar and Marcos Martínez},
  year = {2010},
  doi = {10.1145/1785481.1785529},
  url = {http://doi.acm.org/10.1145/1785481.1785529},
  tags = {caching, modeling},
  researchr = {https://researchr.org/publication/CastilloPVM10},
  cites = {0},
  citedby = {0},
  pages = {191-196},
  booktitle = {Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010},
  editor = {R. Iris Bahar and Fabrizio Lombardi and David Atienza and Erik Brunvand},
  publisher = {ACM},
  isbn = {978-1-4503-0012-4},
}