Fast instruction cache modeling for approximate timed HW/SW co-simulation

Juan Castillo, Hector Posadas, Eugenio Villar, Marcos Martínez. Fast instruction cache modeling for approximate timed HW/SW co-simulation. In R. Iris Bahar, Fabrizio Lombardi, David Atienza, Erik Brunvand, editors, Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010. pages 191-196, ACM, 2010. [doi]

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