A 69 dB SNDR, 25 MHz BW, 800 MS/s Continuous-Time Bandpass ΔΣ Modulator Using a Duty-Cycle-Controlled DAC for Low Power and Reconfigurability

Hyungil Chae, Michael P. Flynn. A 69 dB SNDR, 25 MHz BW, 800 MS/s Continuous-Time Bandpass ΔΣ Modulator Using a Duty-Cycle-Controlled DAC for Low Power and Reconfigurability. J. Solid-State Circuits, 51(3):649-659, 2016. [doi]

@article{ChaeF16,
  title = {A 69 dB SNDR, 25 MHz BW, 800 MS/s Continuous-Time Bandpass ΔΣ Modulator Using a Duty-Cycle-Controlled DAC for Low Power and Reconfigurability},
  author = {Hyungil Chae and Michael P. Flynn},
  year = {2016},
  doi = {10.1109/JSSC.2016.2514442},
  url = {http://dx.doi.org/10.1109/JSSC.2016.2514442},
  researchr = {https://researchr.org/publication/ChaeF16},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {51},
  number = {3},
  pages = {649-659},
}