Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface

Kwanyeob Chae, Billy Koo, Jihun Oh, Sanghune Park, Jongshin Shin, Jaehong Park. Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface. In International SoC Design Conference, ISOCC 2018, Daegu, South Korea, November 12-15, 2018. pages 140-141, IEEE, 2018. [doi]

Abstract

Abstract is missing.