Jonathan Chang, Stefan Rusu, Jonathan Shoemaker, Simon Tam 0001, Ming Huang, Mizan Haque, Siufu Chiu, Kevin Truong, Mesbah Karim, Gloria Leong, Kiran Desai, Richard Goe, Sandhya Kulkarni. A 130-nm triple-V/sub t/ 9-MB third-level on-die cache for the 1.7-GHz Itanium/spl reg/ 2 processor. J. Solid-State Circuits, 40(1):195-203, 2005. [doi]
Abstract is missing.