Ting-Sheng Chao, Yu-lung Lo, Wei-Bin Yang, Kuo-Hsing Cheng. Designing ultra-low voltage PLL Using a bulk-driven technique. In 35th European Solid-State Circuits Conference, ESSCIRC 2009, Athens, Greece, 14-18 September 2009. pages 388-391, IEEE, 2009. [doi]
Abstract is missing.