Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults - researchr publication

researchr

You are not signed in
Sign in
Sign up

Shweta Chary, Michael L. Bushnell. Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. In 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India. pages 413-418, IEEE Computer Society, 2006. [doi]

Abstract is missing.

runs on WebDSL