Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller - researchr publication

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Subhomoy Chattopadhyay, Rakesh Patel. Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller. In 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India. pages 5, IEEE Computer Society, 2007. [doi]

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