Yogesh Chaurasiya, Surabhi Bhargava, Arvind Sharma, Baljit Kaur, Bulusu Anand. Timing model for two stage buffer and its application in ECSM characterization. In 19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015. pages 1-6, IEEE, 2015. [doi]
Abstract is missing.