Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein. Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis. In 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 12-14 March 2006, Berkeley, California, USA. pages 117-128, IEEE Computer Society, 2007. [doi]
Abstract is missing.