High-Speed Pipelined EGG Processor on FPGA

William N. Chelton, Mohammed Benaissa. High-Speed Pipelined EGG Processor on FPGA. In Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada. pages 136-141, IEEE, 2006. [doi]

Abstract

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